27-2 Vol. 3C

VM EXITS

— An external interrupt does not acknowledge the interrupt controller and the interrupt remains pending, 

unless the “acknowledge interrupt on exit” VM-exit control is 1. In such a case, the interrupt controller is 
acknowledged and the interrupt is no longer pending.

— The flags L0 – L3 in DR7 (bit 0, bit 2, bit 4, and bit 6) are not cleared when a task switch causes a VM exit.
— If a task switch causes a VM exit, none of the following are modified by the task switch: old task-state 

segment (TSS); new TSS; old TSS descriptor; new TSS descriptor; RFLAGS.NT

1

; or the TR register.

— No last-exception record is made if the event that would do so directly causes a VM exit. 
— If a machine-check exception causes a VM exit directly, this does not prevent machine-check MSRs from 

being updated. These are updated by the machine-check event itself and not the resulting machine-check 
exception.

— If the logical processor is in an inactive state (see Section 24.4.2) and not executing instructions, some 

events may be blocked but others may return the logical processor to the active state. Unblocked events 
may cause VM exits.

2

 If an unblocked event causes a VM exit directly, a return to the active state occurs 

only after the VM exit completes.

3

 The VM exit generates any special bus cycle that is normally generated 

when the active state is entered from that activity state.
MTF VM exits (see Section 25.5.2 and Section 26.6.8) are not blocked in the HLT activity state. If an MTF 
VM exit occurs in the HLT activity state, the logical processor returns to the active state only after the 
VM exit completes. MTF VM exits are blocked the shutdown state and the wait-for-SIPI state.

•

If an event causes a VM exit indirectly, the event does update architectural state:
— A debug exception updates DR6, DR7, and the IA32_DEBUGCTL MSR. No debug exceptions are considered 

pending.

— A page fault updates CR2.
— An NMI causes subsequent NMIs to be blocked before the VM exit commences.
— An external interrupt acknowledges the interrupt controller and the interrupt is no longer pending.
— If the logical processor had been in an inactive state, it enters the active state and, before the VM exit 

commences, generates any special bus cycle that is normally generated when the active state is entered 
from that activity state.

— There is no blocking by STI or by MOV SS when the VM exit commences.
— Processor state that is normally updated as part of delivery through the IDT (CS, RIP, SS, RSP, RFLAGS) is 

not modified. However, the incomplete delivery of the event may write to the stack.

— The treatment of last-exception records is implementation dependent:

•

Some processors make a last-exception record when beginning the delivery of an event through the IDT 
(before it can encounter a nested exception). Such processors perform this update even if the event 
encounters a nested exception that causes a VM exit (including the case where nested exceptions lead 
to a triple fault).

•

Other processors delay making a last-exception record until event delivery has reached some event 
handler successfully (perhaps after one or more nested exceptions). Such processors do not update the 
last-exception record if a VM exit or triple fault occurs before an event handler is reached.

•

If the “virtual NMIs” VM-execution control is 1, VM entry injects an NMI, and delivery of the NMI causes a 
nested exception, double fault, task switch, or APIC access that causes a VM exit, virtual-NMI blocking is in 
effect before the VM exit commences.

1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX oper-

ation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation refers to the 32-bit 

forms of those registers (EAX, EIP, ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32 

bits of the indicated register.

2. If a VM exit takes the processor from an inactive state resulting from execution of a specific instruction (HLT or MWAIT), the value 

saved for RIP by that VM exit will reference the following instruction.

3. An exception is made if the logical processor had been inactive due to execution of MWAIT; in this case, it is considered to have 

become active before the VM exit.