4-8 Vol. 3A
PAGING
— Bits 11:2 are bits 31:22 of the linear address.
— Bits 1:0 are 0.
Because a PDE is identified using bits 31:22 of the linear address, it controls access to a 4-Mbyte region of the
linear-address space. Use of the PDE depends on CR4.PSE and the PDE’s PS flag (bit 7):
•
If CR4.PSE = 1 and the PDE’s PS flag is 1, the PDE maps a 4-MByte page (see Table 4-4). The final physical
address is computed as follows:
— Bits 39:32 are bits 20:13 of the PDE.
— Bits 31:22 are bits 31:22 of the PDE.
1
— Bits 21:0 are from the original linear address.
•
If CR4.PSE = 0 or the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the physical
address specified in bits 31:12 of the PDE (see Table 4-5). A page table comprises 1024 32-bit entries (PTEs).
A PTE is selected using the physical address defined as follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from the PDE.
— Bits 11:2 are bits 21:12 of the linear address.
— Bits 1:0 are 0.
•
Because a PTE is identified using bits 31:12 of the linear address, every PTE maps a 4-KByte page (see
Table 4-6). The final physical address is computed as follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the entry is used neither to refer-
ence another paging-structure entry nor to map a page. There is no translation for a linear address whose transla-
tion would use such a paging-structure entry; a reference to such a linear address causes a page-fault exception
(see Section 4.7).
With 32-bit paging, there are reserved bits only if CR4.PSE = 1:
•
If the P flag and the PS flag (bit 7) of a PDE are both 1, the bits reserved depend on MAXPHYADDR, and whether
the PSE-36 mechanism is supported:
2
— If the PSE-36 mechanism is not supported, bits 21:13 are reserved.
— If the PSE-36 mechanism is supported, bits 21:(M–19) are reserved, where M is the minimum of 40 and
MAXPHYADDR.
•
If the PAT is not supported:
3
— If the P flag of a PTE is 1, bit 7 is reserved.
— If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.
(If CR4.PSE = 0, no bits are reserved with 32-bit paging.)
A reference using a linear address that is successfully translated to a physical address is performed only if allowed
by the access rights of the translation; see Section 4.6.
1. The upper bits in the final physical address do not all come from corresponding positions in the PDE; the physical-address bits in the
PDE are not all contiguous.
2. See Section 4.1.4 for how to determine MAXPHYADDR and whether the PSE-36 mechanism is supported.
3. See Section 4.1.4 for how to determine whether the PAT is supported.