Vol. 2A 2-39

INSTRUCTION FORMAT

standard modR/M byte’s reg field and rm field and VEX.vvvv. Such a scalar opmask instruction does not 
support conditional update of the destination operand.

•

An opmask register providing conditional processing and/or conditional update of the destination register of a 
vector instruction is encoded using EVEX.aaa field (see Section 2.6.4).

•

An opmask register serving as the destination or source operand of a vector instruction is encoded using 
standard modR/M byte’s reg field and rm fields.

2.6.4 

Masking Support in EVEX

EVEX can encode an opmask register to conditionally control per-element computational operation and updating of 
result of an instruction to the destination operand. The predicate operand is known as the opmask register. The 
EVEX.aaa field, P[18:16] of the EVEX prefix, is used to encode one out of a set of eight 64-bit architectural regis-
ters. Note that from this set of 8 architectural registers, only k1 through k7 can be addressed as predicate oper-
ands. k0 can be used as a regular source or destination but cannot be encoded as a predicate operand. 
AVX-512 instructions support two types of masking with EVEX.z bit (P[23]) controlling the type of masking: 

•

Merging-masking, which is the default type of masking for EVEX-encoded vector instructions, preserves the old 
value of each element of the destination where the corresponding mask bit has a 0. It corresponds to the case 
of EVEX.z = 0.

•

Zeroing-masking, is enabled by having the EVEX.z bit set to 1. In this case, an element of the destination is set 
to 0 when the corresponding mask bit has a 0 value. 

AVX-512 Foundation instructions can be divided into the following groups:

•

Instructions which support “zeroing-masking”.
— Also allow merging-masking.

•

Instructions which require aaa = 000.
— Do not allow any form of masking.

•

Instructions which allow merging-masking but do not allow zeroing-masking.
— Require EVEX.z to be set to 0.
— This group is mostly composed of instructions that write to memory.

•

Instructions which require aaa <> 000 do not allow EVEX.z to be set to 1.
— Allow merging-masking and do not allow zeroing-masking, e.g., gather instructions.

2.6.5 Compressed 

Displacement (disp8*N) Support in EVEX

For memory addressing using disp8 form, EVEX-encoded instructions always use a compressed displacement 
scheme by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length, 
the value of EVEX.b bit (embedded broadcast) and the input element size of the instruction. In general, the factor 
N corresponds to the number of bytes characterizing the internal memory operation of the input operand (e.g., 64 
when the accessing a full 512-bit memory vector). The scale factor N is listed in Table 2-34 and Table 2-35 below, 

Table 2-33.  Opmask Register Specifier Encoding

[2:0]

Register Access

Common Usages 

REG

modrm.reg

k0-k7

Source

NDS

VEX.vvvv

k0-k7

2nd Source 

RM

modrm.r/m

k0-7

1st Source 

{k1}

EVEX.aaa

k0

1

-k7

NOTES:

1. Instructions that overwrite the conditional mask in opmask do not permit using k0 as the embedded mask.

Opmask