Vol. 2A 2-13

INSTRUCTION FORMAT

2.3 

INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)

Intel AVX instructions are encoded using an encoding scheme that combines prefix bytes, opcode extension field, 
operand encoding fields, and vector length encoding capability into a new prefix, referred to as VEX. In the VEX 
encoding scheme, the VEX prefix may be two or three bytes long, depending on the instruction semantics. Despite 
the two-byte or three-byte length of the VEX prefix, the VEX encoding format provides a more compact represen-
tation/packing of the components of encoding an instruction in Intel 64 architecture. The VEX encoding scheme 
also allows more headroom for future growth of Intel 64 architecture.

2.3.1 Instruction 

Format

Instruction encoding using VEX prefix provides several advantages:

•

Instruction syntax support for three operands and up-to four operands when necessary. For example, the third 
source register used by VBLENDVPD is encoded using bits 7:4 of the immediate byte.

•

Encoding support for vector length of 128 bits (using XMM registers) and 256 bits (using YMM registers).

•

Encoding support for instruction syntax of non-destructive source operands.

•

Elimination of escape opcode byte (0FH), SIMD prefix byte (66H, F2H, F3H) via a compact bit field represen-
tation within the VEX prefix.

•

Elimination of the need to use REX prefix to encode the extended half of general-purpose register sets (R8-
R15) for direct register access, memory addressing, or accessing XMM8-XMM15 (including YMM8-YMM15).

•

Flexible and more compact bit fields are provided in the VEX prefix to retain the full functionality provided by 
REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only because only a 
subset of SIMD instructions need them. 

•

Extensibility for future instruction extensions without significant instruction length increase.

Figure 2-8 shows the Intel 64 instruction encoding format with VEX prefix support. Legacy instruction without a 
VEX prefix is fully supported and unchanged. The use of VEX prefix in an Intel 64 instruction is optional, but a VEX 
prefix is required for Intel 64 instructions that operate on YMM registers or support three and four operand syntax. 
VEX prefix is not a constant-valued, “single-purpose” byte like 0FH, 66H, F2H, F3H in legacy SSE instructions. VEX 
prefix provides substantially richer capability than the REX prefix. 

Figure 2-8.  Instruction Encoding Format with VEX Prefix

2.3.2 

VEX and the LOCK prefix

Any VEX-encoded instruction with a LOCK prefix preceding VEX will #UD.

2.3.3 

VEX and the 66H, F2H, and F3H prefixes

Any VEX-encoded instruction with a 66H, F2H, or F3H prefix preceding VEX will #UD.

2.3.4 

VEX and the REX prefix

Any VEX-encoded instruction with a REX prefix proceeding VEX will #UD. 

ModR/M

1

[Prefixes]

[VEX]

OPCODE

[SIB]

[DISP]

[IMM]

2,3

1

0,1

0,1,2,4

0,1

# Bytes