2-12 Vol. 2A

INSTRUCTION FORMAT

2.2.1.6  

RIP-Relative Addressing

A new addressing form, RIP-relative (relative instruction-pointer) addressing, is implemented in 64-bit mode. An 
effective address is formed by adding displacement to the 64-bit RIP of the next instruction.
In IA-32 architecture and compatibility mode, addressing relative to the instruction pointer is available only with 
control-transfer instructions. In 64-bit mode, instructions that use ModR/M addressing can use RIP-relative 
addressing. Without RIP-relative addressing, all ModR/M modes address memory relative to zero. 
RIP-relative addressing allows specific ModR/M modes to address memory relative to the 64-bit RIP using a signed 
32-bit displacement. This provides an offset range of ±2GB from the RIP. Table 2-7 shows the ModR/M and SIB 
encodings for RIP-relative addressing. Redundant forms of 32-bit displacement-addressing exist in the current 
ModR/M and SIB encodings. There is one ModR/M encoding and there are several SIB encodings. RIP-relative 
addressing is encoded using a redundant form. 
In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined to be RIP+Disp32 rather than 
displacement-only. See Table 2-7.

The ModR/M encoding for RIP-relative addressing does not depend on using a prefix. Specifically, the r/m bit field 
encoding of 101B (used to select RIP-relative addressing) is not affected by the REX prefix. For example, selecting 
R13 (REX.B = 1, r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/m field of REX.B 
combined with ModR/M is not fully decoded. In order to address R13 with no displacement, software must encode 
R13 + 0 using a 1-byte displacement of zero. 
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The use of the address-size prefix 
does not disable RIP-relative addressing. The effect of the address-size prefix is to truncate and zero-extend the 
computed effective address to 32 bits. 

2.2.1.7  

Default 64-Bit Operand Size

In 64-bit mode, two groups of instructions have a default operand size of 64 bits (do not need a REX prefix for this 
operand size). These are:

•

Near branches.

•

All instructions, except far branches, that implicitly reference the RSP.

2.2.2 

Additional Encodings for Control and Debug Registers

In 64-bit mode, more encodings for control and debug registers are available. The REX.R bit is used to modify the 
ModR/M reg field when that field encodes a control or debug register (see Table 2-4). These encodings enable the 
processor to address CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit mode. CR8 
becomes the Task Priority Register (TPR). 
In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not implemented. Any attempt to access 
unimplemented registers results in an invalid-opcode exception (#UD).

Table 2-7.  RIP-Relative Addressing

ModR/M and SIB Sub-field Encodings Compatibility Mode 

Operation

64-bit Mode 

Operation

Additional Implications in 64-bit mode

ModR/M Byte mod = 00

Disp32

RIP + Disp32

Must use SIB form with normal (zero-based) 

displacement addressing 

r/m = 101 (none)

SIB Byte

base = 101 (none)

if mod = 00, Disp32 Same as legacy None

index = 100 (none)
scale = 0, 1, 2, 4