CPUID—CPU Identification

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-189

CPUID—CPU Identification

Instruction Operand Encoding

Description

The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can 
set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction 
operates the same in non-64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.

1

 The 

instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well). 
For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value 
and the Vendor Identification String in the appropriate registers:

MOV EAX, 00H
CPUID

Table 3-8 shows information returned, depending on the initial value loaded into the EAX register. 
Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX 
is higher than the maximum input value for basic or extended function for that processor then the data for the 
highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:

CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *) 
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *) 
CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *) 
CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *) 
CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)

If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on 
that processor then 0 is returned in all the registers.
When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence 
on input ECX value in the basic leaf is honored.
CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution 
guarantees that any modifications to flags, registers, and memory for previous instructions are completed before 
the next instruction is fetched and executed.
See also: 
“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3A.
“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3A.

Opcode

Instruction

Op/ 

En

64-Bit 

Mode

Compat/

Leg Mode

Description

0F A2

CPUID

NP

Valid

Valid

Returns processor identification and feature 

information to the EAX, EBX, ECX, and EDX 

registers, as determined by input entered in 

EAX (in some cases, ECX as well).

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

NP

NA

NA

NA

NA

1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.