Vol. 2A 2-41

INSTRUCTION FORMAT

2.6.6 

EVEX Encoding of Broadcast/Rounding/SAE Support

EVEX.b can provide three types of encoding context, depending on the instruction classes:

•

Embedded broadcasting of one data element from a source memory operand to the destination for vector 
instructions with “load+op” semantic.

•

Static rounding control overriding MXCSR.RC for floating-point instructions with rounding semantic.

•

“Suppress All exceptions” (SAE) overriding MXCSR mask control for floating-point arithmetic instructions that 
do not have rounding semantic.

2.6.7 

Embedded Broadcast Support in EVEX

EVEX encodes an embedded broadcast functionality that is supported on many vector instructions with 32-bit 
(double word or single-precision floating-point) and 64-bit data elements, and when the source operand is from 
memory. EVEX.b (P[20]) bit is used to enable broadcast on load-op instructions. When enabled, only one element 
is loaded from memory and broadcasted to all other elements instead of loading the full memory size. 
The following instruction classes do not support embedded broadcasting:

•

Instructions with only one scalar result is written to the vector destination.

•

Instructions with explicit broadcast functionality provided by its opcode.

•

Instruction semantic is a pure load or a pure store operation.

2.6.8 

Static Rounding Support in EVEX

Static rounding control embedded in the EVEX encoding system applies only to register-to-register flavor of 
floating-point instructions with rounding semantic at two distinct vector lengths: (i) scalar, (ii) 512-bit. In both 
cases, the field EVEX.L’L expresses rounding mode control overriding MXCSR.RC if EVEX.b is set. When EVEX.b is 
set, “suppress all exceptions” is implied. The processor behave as if all MXCSR masking controls are set.

2.6.9 

SAE Support in EVEX

The EVEX encoding system allows arithmetic floating-point instructions without rounding semantic to be encoded 
with the SAE attribute. This capability applies to scalar and 512-bit vector lengths, register-to-register only, by 
setting EVEX.b. When EVEX.b is set, “suppress all exceptions” is implied. The processor behaves as if all MXCSR 
masking controls are set.

2.6.10 

Vector Length Orthogonality 

The architecture of EVEX encoding scheme can support SIMD instructions operating at multiple vector lengths. 
Many AVX-512 Foundation instructions operate at 512-bit vector length. The vector length of EVEX encoded vector 
instructions are generally determined using the L’L field in EVEX prefix, except for 512-bit floating-point, reg-reg 
instructions with rounding semantic. The table below shows the vector length corresponding to various values of 
the L’L bits. When EVEX is used to encode scalar instructions, L’L is generally ignored.
When EVEX.b bit is set for a register-register instructions with floating-point rounding semantic, the same two bits 
P2[6:5] specifies rounding mode for the instruction, with implied SAE behavior. The mapping of different instruc-
tion classes relative to the embedded broadcast/rounding/SAE control and the EVEX.L’L fields are summarized in 
Table 2-36.