Vol. 1 D-1

APPENDIX D

GUIDELINES FOR WRITING X87 FPU

EXCEPTION HANDLERS

As described in Chapter 8, “Programming with the x87 FPU,” the IA-32 Architecture supports two mechanisms for 
accessing exception handlers to handle unmasked x87 FPU exceptions: native mode and MS-DOS compatibility 
mode. The primary purpose of this appendix is to provide detailed information to help software engineers design 
and write x87 FPU exception-handling facilities to run on PC systems that use the MS-DOS compatibility mode

1

 for 

handling x87 FPU exceptions. Some of the information in this appendix will also be of interest to engineers who are 
writing native-mode x87 FPU exception handlers. The information provided is as follows:

•

Discussion of the origin of the MS-DOS x87 FPU exception handling mechanism and its relationship to the x87 
FPU’s native exception handling mechanism.

•

Description of the IA-32 flags and processor pins that control the MS-DOS x87 FPU exception handling 
mechanism.

•

Description of the external hardware typically required to support MS-DOS exception handling mechanism.

•

Description of the x87 FPU’s exception handling mechanism and the typical protocol for x87 FPU exception 
handlers.

•

Code examples that demonstrate various levels of x87 FPU exception handlers.

•

Discussion of x87 FPU considerations in multitasking environments.

•

Discussion of native mode x87 FPU exception handling.

The information given is oriented toward the most recent generations of IA-32 processors, starting with the 
Intel486. It is intended to augment the reference information given in Chapter 8, “Programming with the x87 FPU.”
A more extensive version of this appendix is available in the application note AP-578, Software and Hardware 
Considerations for x87 FPU Exception Handlers for Intel Architecture Processors (Order Number 243291), which is 
available from Intel.

D.1 MS-DOS 

COMPATIBILITY 

SUB-MODE FOR HANDLING X87 FPU EXCEPTIONS

The first generations of IA-32 processors (starting with the Intel 8086 and 8088 processors and going through the 
Intel 286 and Intel386 processors) did not have an on-chip floating-point unit. Instead, floating-point capability 
was provided on a separate numeric coprocessor chip. The first of these numeric coprocessors was the Intel 8087, 
which was followed by the Intel 287 and Intel 387 numeric coprocessors. 
To allow the 8087 to signal floating-point exceptions to its companion 8086 or 8088, the 8087 has an output pin, 
INT, which it asserts when an unmasked floating-point exception occurs. The designers of the 8087 recommended 
that the output from this pin be routed through a programmable interrupt controller (PIC) such as the Intel 8259A 
to the INTR pin of the 8086 or 8088. The handler for the resulting interrupt could then be used to access the 
floating-point exception handler.
However, the original IBM* PC design and MS-DOS operating system used a different mechanism for handling the 
INT output from the 8087. It connected the INT pin directly to the NMI input pin of the 8086 or 8088. The NMI inter-
rupt handler then had to determine if the interrupt was caused by a floating-point exception or another NMI event. 
This mechanism is the origin of what is now called the “MS-DOS compatibility mode.” The decision to use this latter 
floating-point exception handling mechanism came about because when the IBM PC was first designed, the 8087 
was not available. When the 8087 did become available, other functions had already been assigned to the eight 
inputs to the PIC. One of these functions was a BIOS video interrupt, which was assigned vector 16 for the 8086 
and 8088.

1  Microsoft Windows* 95 and Windows 3.1 (and earlier versions) operating systems use almost the same x87 FPU exception handling 

interface as MS-DOS. The recommendations in this appendix for a MS-DOS compatible exception handler thus apply to all three oper-

ating systems.