18-2 Vol. 1

INPUT/OUTPUT

single bus cycle. Likewise, 32-bit ports should be aligned to addresses that are multiples of four (0, 4, 8, ...). The 
processor supports data transfers to unaligned ports, but there is a performance penalty because one or more 
extra bus cycle must be used.
The exact order of bus cycles used to access unaligned ports is undefined and is not guaranteed to remain the same 
in future IA-32 processors. If hardware or software requires that I/O ports be written to in a particular order, that 
order must be specified explicitly. For example, to load a word-length I/O port at address 2H and then another word 
port at 4H, two word-length writes must be used, rather than a single doubleword write at 2H.
Note that the processor does not mask parity errors for bus cycles to the I/O address space. Accessing I/O ports 
through the I/O address space is thus a possible source of parity errors.

18.3.1 Memory-Mapped 

I/O

I/O devices that respond like memory components can be accessed through the processor’s physical-memory 
address space (see Figure 18-1). When using memory-mapped I/O, any of the processor’s instructions that refer-
ence memory can be used to access an I/O port located at a physical-memory address. For example, the MOV 
instruction can transfer data between any register and a memory-mapped I/O port. The AND, OR, and TEST 
instructions may be used to manipulate bits in the control and status registers of a memory-mapped peripheral 
device.
When using memory-mapped I/O, caching of the address space mapped for I/O operations must be prevented. 
With the Pentium 4, Intel Xeon, and P6 family processors, caching of I/O accesses can be prevented by using 
memory type range registers (MTRRs) to map the address space used for the memory-mapped I/O as uncacheable 
(UC). See Chapter 11, “Memory Cache Control” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for a complete discussion of the MTRRs.
The Pentium and Intel486 processors do not support MTRRs. Instead, they provide the KEN# pin, which when held 
inactive (high) prevents caching of all addresses sent out on the system bus. To use this pin, external address 
decoding logic is required to block caching in specific address spaces.

All the IA-32 processors that have on-chip caches also provide the PCD (page-level cache disable) flag in page table 
and page directory entries. This flag allows caching to be disabled on a page-by-page basis. See “Page-Directory 
and Page-Table Entries” in Chapter 4 of in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3A.

Figure 18-1.  Memory-Mapped I/O

FFFF 

I/O Port

EPROM

RAM

Physical Memory

0

I/O Port
I/O Port