Vol. 1 18-1

CHAPTER 18

INPUT/OUTPUT

In addition to transferring data to and from external memory, IA-32 processors can also transfer data to and from 
input/output ports (I/O ports). I/O ports are created in system hardware by circuity that decodes the control, data, 
and address pins on the processor. These I/O ports are then configured to communicate with peripheral devices. An 
I/O port can be an input port, an output port, or a bidirectional port. Some I/O ports are used for transmitting data, 
such as to and from the transmit and receive registers, respectively, of a serial interface device. Other I/O ports are 
used to control peripheral devices, such as the control registers of a disk controller.
This chapter describes the processor’s I/O architecture. The topics discussed include:

•

I/O port addressing

•

I/O instructions

•

I/O protection mechanism

18.1 

I/O PORT ADDRESSING

The processor permits applications to access I/O ports in either of two ways:

•

Through a separate I/O address space

•

Through memory-mapped I/O

Accessing I/O ports through the I/O address space is handled through a set of I/O instructions and a special I/O 
protection mechanism. Accessing I/O ports through memory-mapped I/O is handled with the processor’s general-
purpose move and string instructions, with protection provided through segmentation or paging. I/O ports can be 
mapped so that they appear in the I/O address space or the physical-memory address space (memory mapped 
I/O) or both.
One benefit of using the I/O address space is that writes to I/O ports are guaranteed to be completed before the 
next instruction in the instruction stream is executed. Thus, I/O writes to control system hardware cause the hard-
ware to be set to its new state before any other instructions are executed. See Section 18.6, “Ordering I/O,” for 
more information on serializing of I/O operations.

18.2 

I/O PORT HARDWARE

From a hardware point of view, I/O addressing is handled through the processor’s address lines. For the P6 family, 
Pentium 4, and Intel Xeon processors, the request command lines signal whether the address lines are being driven 
with a memory address or an I/O address; for Pentium processors and earlier IA-32 processors, the M/IO# pin indi-
cates a memory address (1) or an I/O address (0). When the separate I/O address space is selected, it is the 
responsibility of the hardware to decode the memory-I/O bus transaction to select I/O ports rather than memory. 
Data is transmitted between the processor and an I/O device through the data lines.

18.3 

I/O ADDRESS SPACE

The processor’s I/O address space is separate and distinct from the physical-memory address space. The I/O 
address space consists of 2

16

 (64K) individually addressable 8-bit I/O ports, numbered 0 through FFFFH. I/O port 

addresses 0F8H through 0FFH are reserved. Do not assign I/O ports to these addresses. The result of an attempt 
to address beyond the I/O address space limit of FFFFH is implementation-specific; see the Developer’s Manuals for 
specific processors for more details.
Any two consecutive 8-bit ports can be treated as a 16-bit port, and any four consecutive ports can be a 32-bit port. 
In this manner, the processor can transfer 8, 16, or 32 bits to or from a device in the I/O address space. Like words 
in memory, 16-bit ports should be aligned to even addresses (0, 2, 4, ...) so that all 16 bits can be transferred in a