15-12 Vol. 1

PROGRAMMING WITH INTEL® AVX-512

15.6.4 

STATIC ROUNDING MODE AND SUPPRESS ALL EXCEPTIONS

In previous SIMD instruction extensions (up to AVX and AVX2), rounding control is generally specified in MXCSR, 
with a handful of instructions providing per-instruction rounding override via encoding fields within the imm8 
operand. AVX-512 offers a more flexible encoding attribute to override MXCSR-based rounding control for floating-
pointing instructions with rounding semantics. This rounding attribute embedded in the EVEX prefix is called Static 
(per instruction) Rounding Mode or Rounding Mode override. This attribute allows programmers to statically apply 
a specific arithmetic rounding mode irrespective of the value of RM bits in MXCSR. It is available only to register-
to-register flavors of EVEX-encoded floating-point instructions with rounding semantic. The differences between 
these three rounding control interfaces are summarized in Table 15-4. 

The static rounding-mode override in AVX-512 also implies the “suppress-all-exceptions” (SAE) attribute. The SAE 
effect is as if all the MXCSR mask bits are set, and none of the MXCSR flags will be updated. Using static rounding-
mode via EVEX without SAE is not supported.
Static Rounding Mode and SAE control can be enabled in the encoding of the instruction by setting the EVEX.b bit 
to 1 in a register-register vector instruction. In such a case, vector length is assumed to be MAX_VL (512-bit in 
case of AVX-512 packed vector instructions) or 128-bit for scalar instructions. Table 15-5 summarizes the possible 
static rounding-mode assignments in AVX-512 instructions.
Note that some instructions already allow specifying the rounding mode statically via immediate bits. In such 
cases, the immediate bits take precedence over the embedded rounding mode (in the same vein that they take 
precedence over whatever MXCSR.RM says).

An example of use would be as follows:

vaddps zmm7 {k6}, zmm2, zmm4, {rd-sae}

This would perform the single-precision floating-point addition of vectors zmm2 and zmm4 with round-towards-
minus-infinity, leaving the result in vector zmm7 using k6 as conditional writemask.

Table 15-4.  Characteristics of Three Rounding Control Interfaces

Rounding Interface

Static Rounding 

Override

Imm8 Embedded Rounding 

Override

MXCSR Rounding Control

Semantic Requirement

FP rounding

FP rounding

FP rounding

Prefix Requirement

EVEX.B = 1

NA

NA

Rounding Control

EVEX.L’L

IMM8[1:0] or MXCSR.RC

(depending on IMM8[2])

MXCSR.RC

Suppress All Exceptions (SAE)

Implied

no

no

SIMD FP Exception #XF

All suppressed

Can raise #I, #P (unless SPE is set) MXCSR masking controls

MXCSR flag update

No

yes (except PE if SPE is set) 

Yes

Precedence

Above MXCSR.RC

Above EVEX.L’L

Default

Scope

512-bit, reg-reg, 

Scalar reg-reg

ROUNDPx, ROUNDSx, 

VCVTPS2PH, VRNDSCALExx

All SIMD operands, vector lengths

Table 15-5.  Static Rounding Mode

Function

Description

{rn-sae}

Round to nearest (even) + SAE

{rd-sae}

Round down (toward -inf) + SAE

{ru-sae}

Round up (toward +inf) + SAE

{rz-sae}

Round toward zero (Truncate) + SAE