Vol. 1 15-7

PROGRAMMING WITH INTEL® AVX-512

The AVX512VL flag alone is never sufficient to determine a given Intel AVX-512 instruction may be encoded at 
vector lengths smaller than 512 bits. Software must use the procedure described in Figure 15-5 and Table 15-2.

To illustrate the procedure described in Figure 15-5 and Table 15-2 for software to use EVEX.256 encoded VPCON-
FLICT, the following sequence is provided. It is strongly recommended this sequence is followed.
1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2) Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and 
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by 
OS).
3) Verify CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512CD[bit 28] = 1, and 
CPUID.0x7.0:EBX.AVX512VL[bit 31] = 1.

In some specific cases, AVX512VL may only support EVEX.256 encoding but not EVEX.128. These cases are listed 
in Table 15-3.

Figure 15-5.  Procedural Flow for Detection of Intel AVX-512 Instructions Operating at Vector Lengths < 512

Table 15-2.  Feature flag Collection Required of 256/128 Bit Vector Lengths for Each Instruction Group 

Usage of 256/128 Vector Lengths

Feature Flag Collection to Verify

AVX512F 

AVX512F & AVX512VL

AVX512CD

AVX512F & AVX512CD & AVX512VL

AVX512DQ

AVX512F & 

AVX512DQ & AVX512VL

AVX512BW

AVX512F & 

AVX512BW & AVX512VL

Implied HW support for

Check enabled state in

XCR0 via XGETBV

Check applicable collection of

CPUID flags listed in 

Table 2-2

Check feature flag

CPUID.1H:ECX.OXSAVE = 1? 

OS provides processor

extended state management

States

ok to use

XSAVE, XRSTOR, XGETBV, XCR0

enabled

Instructions

Yes 

YMM,ZMM

Opmask,