Vol. 1 15-3

PROGRAMMING WITH INTEL® AVX-512

Note that some SIMD instructions supporting three-operand syntax but processing only less than or equal to 128-
bits of data are considered part of the 512-bit SIMD instruction set extensions, because bits MAX_VL-1:128 of the 
destination register are zeroed by the processor. The same rule applies to instructions operating on 256-bits of data 
where bits MAX_VL-1:256 of the destination register are zeroed.

15.1.5 

EVEX Instruction Encoding Support

Intel AVX-512 instructions employ a new encoding prefix, referred to as EVEX, in the Intel 64 and IA-32 instruction 
encoding format. Instruction encoding using the EVEX prefix provides the following capabilities:

•

Direct encoding of a SIMD register operand within EVEX (similar to VEX). This provides instruction syntax 
support for three source operands. 

•

Compaction of REX prefix functionality and extended SIMD register encoding: the equivalent REX-prefix 
compaction functionality offered by the VEX prefix is provided within EVEX. Furthermore, EVEX extends the 
operand encoding capability to allow direct addressing of up to 32 ZMM registers in 64-bit mode.

•

Compaction of SIMD prefix functionality and escape byte encoding: the functionality of a SIMD prefix (66H, 
F2H, F3H) on opcode is equivalent to an opcode extension field to introduce new processing primitives. This 
functionality is provided in the VEX prefix encoding scheme and employed within the EVEX prefix. Similarly, the 
functionality of the escape opcode byte (0FH) and two-byte escape (0F38H, 0F3AH) are also compacted within 
the EVEX prefix encoding. 

•

Most EVEX-encoded SIMD numeric and data processing instruction semantics with memory operands have 
more relaxed memory alignment requirements than instructions encoded using SIMD prefixes (see Section 
2.6, “Memory Alignment” in the Intel® Architecture Instruction Set Extensions Programming Reference).

•

Direct encoding of an opmask operand within the EVEX prefix. This provides instruction syntax support for 
conditional vector-element operation and merging of destination operand using an opmask register (k1-k7).

•

Direct encoding of a broadcast attribute for instructions with a memory operand source. This provides 
instruction syntax support for elements broadcasting the second operand before being used in the actual 
operation.

•

Compressed memory address displacements for a more compact instruction encoding byte sequence.

EVEX encoding applies to SIMD instructions operating on XMM, YMM and ZMM registers. EVEX is not supported for 
instructions operating on MMX or x87 registers. Details of EVEX instruction encoding are discussed in Section 2.6, 
“Intel® AVX-512 Encoding” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

15.2 

DETECTION OF AVX-512 FOUNDATION INSTRUCTIONS 

The majority of AVX-512 Foundation instructions are encoded using the EVEX encoding scheme. EVEX-encoded 
instructions can operate on the 512-bit ZMM register state plus 8 opmask registers. The opmask instructions in 
AVX-512 Foundation instructions operate only on opmask registers or with a general purpose register. System 
software requirements to support the ZMM state and opmask instructions are described in Chapter 3, “System 
Programming For Intel® AVX-512” of the Intel® Architecture Instruction Set Extensions Programming Reference.
Processor support of AVX-512 Foundation instructions is indicated by CPUID.(EAX=07H, ECX=0):EBX.AVX512F[bit 
16] = 1. Detection of AVX-512 Foundation instructions operating on ZMM states and opmask registers needs to 
follow the general procedural flow in Figure 15-2.