Vol. 1 13-3

MANAGING STATE USING THE XSAVE FEATURE SET

— If this bit is 0, the processor does not support any of the following instructions: XGETBV, XRSTOR, 

XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV; the processor provides no further 
enumeration through CPUID function 0DH (see below).

— If this bit is 1, the processor supports the following instructions: XGETBV, XRSTOR, XSAVE, and XSETBV.

1

 

Further enumeration is provided through CPUID function 0DH.

CR4.OSXSAVE can be set to 1 if and only if CPUID.1:ECX.XSAVE[bit 26] is enumerated as 1.

•

CPUID function 0DH enumerates details of CPU support through a set of sub-functions. Software selects a 
specific sub-function by the value placed in the ECX register. The following items provide specific details:
— CPUID function 0DH, sub-function 0.

•

EDX:EAX is a bitmap of all the user state components that can be managed using the XSAVE feature 
set. A bit can be set in XCR0 if and only if the corresponding bit is set in this bitmap. Every processor 
that supports the XSAVE feature set will set EAX[0] (x87 state) and EAX[1] (SSE state).
If EAX[i] =  1  (for  1 <  i < 32) or EDX[i–32] = 1 (for 32 ≤ i < 63), sub-function i enumerates details for 
state component i (see below).

•

ECX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all 
the user state components supported by this processor.

•

EBX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all 
the user state components corresponding to bits currently set in XCR0.

— CPUID function 0DH, sub-function 1.

•

EAX[0] enumerates support for the XSAVEOPT instruction. The instruction is supported if and only if 
this bit is 1. If EAX[0] = 0, execution of XSAVEOPT causes an invalid-opcode exception (#UD).

•

EAX[1] enumerates support for compaction extensions to the XSAVE feature set. The following are 
supported if this bit is 1:

—

The compacted format of the extended region of XSAVE areas (see Section 13.4.3). 

—

The XSAVEC instruction. If EAX[1] = 0, execution of XSAVEC causes a #UD.

—

Execution of the compacted form of XRSTOR (see Section 13.8).

•

EAX[2] enumerates support for execution of XGETBV with ECX = 1. This allows software to determine 
the state of the init optimization. See Section 13.6.

•

EAX[3] enumerates support for XSAVES, XRSTORS, and the IA32_XSS MSR. If EAX[3] = 0, execution 
of XSAVES or XRSTORS causes a #UD; an attempt to access the IA32_XSS MSR using RDMSR or 
WRMSR causes a general-protection exception (#GP). Every processor that supports a supervisor state 
component sets EAX[3]. Every processor that sets EAX[3] (XSAVES, XRSTORS, IA32_XSS) will also set 
EAX[1] (the compaction extensions).

•

EAX[31:4] are reserved.

•

EBX enumerates the size (in bytes) required by the XSAVES instruction for an XSAVE area containing all 
the state components corresponding to bits currently set in XCR0 | IA32_XSS.

•

EDX:ECX is a bitmap of all the supervisor state components that can be managed by XSAVES and 
XRSTORS. A bit can be set in the IA32_XSS MSR if and only if the corresponding bit is set in this bitmap.

NOTE

In summary, the XSAVE feature set supports state component i (0 ≤ i < 63) if one of the following 
is true: (1) i < 32 and CPUID.(EAX=0DH,ECX=0):EAX[i] =  1;  (2) i ≥ 32 and 
CPUID.(EAX=0DH,ECX=0):EAX[i–32] = 1; (3) i < 32 and CPUID.(EAX=0DH,ECX=1):ECX[i] =  1; 
or (4) i ≥ 32 and CPUID.(EAX=0DH,ECX=1):EDX[i–32] = 1. The XSAVE feature set supports user 
state component i if (1) or (2) holds; if (3) or (4) holds, state component i is a supervisor state 
component and support is limited to XSAVES and XRSTORS.

1. If CPUID.1:ECX.XSAVE[bit 26] = 1, XGETBV and XSETBV may be executed with ECX = 0 (to read and write XCR0). Any support for 

execution of these instructions with other values of ECX is enumerated separately.