11-10 Vol. 1

PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)

are housed in XMM registers, MMX registers, general registers or memory (at most one operand can reside in 
memory; the destination is always an XMM, MMX, or general register).
The CVTPD2PI (convert packed double-precision floating-point values to packed doubleword integers) instruction 
converts two packed double-precision floating-point numbers to two packed signed doubleword integers, with the 
result stored in an MMX register. When rounding to an integer value, the source value is rounded according to the 
rounding mode in the MXCSR register. The CVTTPD2PI (convert with truncation packed double-precision floating-
point values to packed doubleword integers) instruction is similar to the CVTPD2PI instruction except that trunca-
tion is used to round a source value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 
Conversion Instructions”).
The CVTPI2PD (convert packed doubleword integers to packed double-precision floating-point values) instruction 
converts two packed signed doubleword integers to two double-precision floating-point values. 
The CVTPD2DQ (convert packed double-precision floating-point values to packed doubleword integers) instruction 
converts two packed double-precision floating-point numbers to two packed signed doubleword integers, with the 
result stored in the low quadword of an XMM register. When rounding an integer value, the source value is rounded 
according to the rounding mode selected in the MXCSR register. The CVTTPD2DQ (convert with truncation packed 
double-precision floating-point values to packed doubleword integers) instruction is similar to the CVTPD2DQ 
instruction except that truncation is used to round a source value to an integer value (see Section 4.8.4.2, “Trun-
cation with SSE and SSE2 Conversion Instructions”).
The CVTDQ2PD (convert packed doubleword integers to packed double-precision floating-point values) instruction 
converts two packed signed doubleword integers located in the low-order doublewords of an XMM register to two 
double-precision floating-point values. 
The CVTSD2SI (convert scalar double-precision floating-point value to doubleword integer) instruction converts a 
double-precision floating-point value to a doubleword integer, and stores the result in a general-purpose register. 
When rounding an integer value, the source value is rounded according to the rounding mode selected in the 
MXCSR register. The CVTTSD2SI (convert with truncation scalar double-precision floating-point value to double-
word integer) instruction is similar to the CVTSD2SI instruction except that truncation is used to round the source 
value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).
The CVTSI2SD (convert doubleword integer to scalar double-precision floating-point value) instruction converts a 
signed doubleword integer in a general-purpose register to a double-precision floating-point number, and stores 
the result in an XMM register. 
Conversion between single-precision floating-point and doubleword integer formats — These instruc-
tions convert between packed single-precision floating-point and packed doubleword integer formats. Operands 
are housed in XMM registers, MMX registers, general registers, or memory (the latter for at most one source 
operand). The destination is always an XMM, MMX, or general register. These SSE2 instructions supplement 
conversion instructions (CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSI2SS, CVTSS2SI, and CVTTSS2SI) introduced 
with SSE extensions.
The CVTPS2DQ (convert packed single-precision floating-point values to packed doubleword integers) instruction 
converts four packed single-precision floating-point values to four packed signed doubleword integers, with the 
source and destination operands in XMM registers or memory (the latter for at most one source operand). When 
the conversion is inexact, the rounded value according to the rounding mode selected in the MXCSR register is 
returned. The CVTTPS2DQ (convert with truncation packed single-precision floating-point values to packed double-
word integers) instruction is similar to the CVTPS2DQ instruction except that truncation is used to round a source 
value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).
The CVTDQ2PS (convert packed doubleword integers to packed single-precision floating-point values) instruction 
converts four packed signed doubleword integers to four packed single-precision floating-point numbers, with the 
source and destination operands in XMM registers or memory (the latter for at most one source operand). When 
the conversion is inexact, the rounded value according to the rounding mode selected in the MXCSR register is 
returned. 

11.4.2 

SSE2 64-Bit and 128-Bit SIMD Integer Instructions

SSE2 extensions add several 128-bit packed integer instructions to the IA-32 architecture. Where appropriate, a 
64-bit version of each of these instructions is also provided. The 128-bit versions of instructions operate on data in 
XMM registers; 64-bit versions operate on data in MMX registers. The instructions follow.