Vol. 1 10-17

PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)

10.5.3 

Operation of FXRSTOR

The FXRSTOR instruction takes a single memory operand, which is an FXSAVE area. If the value at bytes 27:24 of 
the FXSAVE area is not a legal value for the MXCSR register (e.g., the value sets reserved bits). Otherwise, the 
instruction loads x87 state and SSE state rom the FXSAVE area. See Section 10.5.1.1 and Section 10.5.1.2 for 
details regarding mode-specific operation and operation determined by instruction prefixes.

10.6 

HANDLING SSE INSTRUCTION EXCEPTIONS

See Section 11.5, “SSE, SSE2, and SSE3 Exceptions,” for a detailed discussion of the general and SIMD floating-
point exceptions that can be generated with the SSE instructions and for guidelines for handling these exceptions 
when they occur.

10.7 WRITING 

APPLICATIONS WITH THE SSE EXTENSIONS

See Section 11.6, “Writing Applications with SSE/SSE2 Extensions,” for additional information about writing appli-
cations and operating-system code using the SSE extensions.