Vol. 1 8-11

PROGRAMMING WITH THE X87 FPU

The fopcode compatibility mode should be enabled only when x87 FPU floating-point exception handlers are 
designed to use the fopcode to analyze program performance or restart a program after an exception has been 
handled.
More recent Intel 64 processors do not support fopcode compatibility mode and do not allow software to set bit 2 
of the IA32_MISC_ENABLE MSR.

8.1.10 

Saving the x87 FPU’s State with FSTENV/FNSTENV and FSAVE/FNSAVE

The FSTENV/FNSTENV and FSAVE/FNSAVE instructions store x87 FPU state information in memory for use by 
exception handlers and other system and application software. The FSTENV/FNSTENV instruction saves the 
contents of the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, and opcode registers. The 
FSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPU data registers. Note that the 
FSAVE/FNSAVE instruction also initializes the x87 FPU to default values (just as the FINIT/FNINIT instruction does) 
after it has saved the original state of the x87 FPU.
The manner in which this information is stored in memory depends on the operating mode of the processor 
(protected mode or real-address mode) and on the operand-size attribute in effect (32-bit or 16-bit). See Figures 
8-9 through 8-12. In virtual-8086 mode or SMM, the real-address mode formats shown in Figure 8-12 is used. See 
Chapter 34, “System Management Mode,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3C, for information on using the x87 FPU while in SMM.
The FLDENV and FRSTOR instructions allow x87 FPU state information to be loaded from memory into the x87 FPU. 
Here, the FLDENV instruction loads only the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, 
and opcode registers, and the FRSTOR instruction loads all the x87 FPU registers, including the x87 FPU stack 
registers. 

Figure 8-9.  Protected Mode x87 FPU State Image in Memory, 32-Bit Format

0

31

0

4

8

12

16

20

24

32-Bit Protected Mode Format

Control Word

Bits 10:0 of opcode

Status Word

Tag Word

FPU Instruction Pointer Selector

FPU Data Pointer Selector (FDS)

FPU Data Pointer Offset (FDP)

0 0 0 0 0

FPU Instruction Pointer Offset (FIP)

16

15

For instructions that also store x87 FPU data registers, the eight 

80-bit registers (R0-R7) follow the above structure in sequence.