6-10 Vol. 1

PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS

The processor responds to interrupts and exceptions in essentially the same way. When an interrupt or exception 
is signaled, the processor halts execution of the current program or task and switches to a handler procedure that 
has been written specifically to handle the interrupt or exception condition. The processor accesses the handler 
procedure through an entry in the interrupt descriptor table (IDT). When the handler has completed handling the 
interrupt or exception, program control is returned to the interrupted program or task.
The operating system, executive, and/or device drivers normally handle interrupts and exceptions independently 
from application programs or tasks. Application programs can, however, access the interrupt and exception 
handlers incorporated in an operating system or executive through assembly-language calls. The remainder of this 
section gives a brief overview of the processor’s interrupt and exception handling mechanism. See Chapter 6, 
“Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
3A, for a description of this mechanism.
The IA-32 Architecture defines 18 predefined interrupts and exceptions and 224 user defined interrupts, which are 
associated with entries in the IDT. Each interrupt and exception in the IDT is identified with a number, called a 
vector. Table 6-1 lists the interrupts and exceptions with entries in the IDT and their respective vectors. Vectors 0 
through 8, 10 through 14, and 16 through 19 are the predefined interrupts and exceptions; vectors 32 through 255 
are for software-defined interrupts, which are for either software interrupts or maskable hardware inter-
rupts.
Note that the processor defines several additional interrupts that do not point to entries in the IDT; the most 
notable of these interrupts is the SMI interrupt. See Chapter 6, “Interrupt and Exception Handling,” in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the interrupts 
and exceptions.
When the processor detects an interrupt or exception, it does one of the following things:

•

Executes an implicit call to a handler procedure.

•

Executes an implicit call to a handler task.

6.4.1 

Call and Return Operation for Interrupt or Exception Handling Procedures

A call to an interrupt or exception handler procedure is similar to a procedure call to another protection level (see 
Section 6.3.6, “CALL and RET Operation Between Privilege Levels”). Here, the vector references one of two kinds 
of gates in the IDT: an interrupt gate or a trap gate. Interrupt and trap gates are similar to call gates in that they 
provide the following information:

•

Access rights information

•

The segment selector for the code segment that contains the handler procedure

•

An offset into the code segment to the first instruction of the handler procedure

The difference between an interrupt gate and a trap gate is as follows. If an interrupt or exception handler is called 
through an interrupt gate, the processor clears the interrupt enable (IF) flag in the EFLAGS register to prevent 
subsequent interrupts from interfering with the execution of the handler. When a handler is called through a trap 
gate, the state of the IF flag is not changed.

Table 6-1.  Exceptions and Interrupts

Vector

Mnemonic

Description

Source

 0

#DE

Divide Error

DIV and IDIV instructions.

 1

#DB

Debug

Any code or data reference.

 2

NMI Interrupt

Non-maskable external interrupt.

 

3

#BP

Breakpoint

INT  3  instruction.

 

4

#OF

Overflow

INTO  instruction.

 5

#BR

BOUND Range Exceeded

BOUND instruction.

 6

#UD

Invalid Opcode (UnDefined Opcode)

UD2 instruction or reserved opcode.

1

 7

#NM

Device Not Available (No Math Coprocessor)

Floating-point or WAIT/FWAIT instruction.