Vol. 1 5-27

INSTRUCTION SET SUMMARY

5.11.2 Packed 

Comparison 

SIMD integer Instruction

PCMPGTQ

Performs logical compare of greater-than on packed integer quadwords.

5.12 

AESNI AND PCLMULQDQ

Six AESNI instructions operate on XMM registers to provide accelerated primitives for block encryption/decryption 
using Advanced Encryption Standard (FIPS-197). The PCLMULQDQ instruction performs carry-less multiplication 
for two binary numbers up to 64-bit wide. 
AESDEC

Perform an AES decryption round using an 128-bit state and a round key.

AESDECLAST

Perform the last AES decryption round using an 128-bit state and a round key.

AESENC

Perform an AES encryption round using an 128-bit state and a round key.

AESENCLAST

Perform the last AES encryption round using an 128-bit state and a round key.

AESIMC

Perform an inverse mix column transformation primitive.

AESKEYGENASSIST

Assist the creation of round keys with a key expansion schedule.

PCLMULQDQ

Perform carryless multiplication of two 64-bit numbers.

5.13 

INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)

Intel

®

 Advanced Vector Extensions (AVX) promotes legacy 128-bit SIMD instruction sets that operate on XMM 

register set to use a “vector extension“ (VEX) prefix and operates on 256-bit vector registers (YMM). Almost all 
prior generations of 128-bit SIMD instructions that operates on XMM (but not on MMX registers) are promoted to 
support three-operand syntax with VEX-128 encoding.
VEX-prefix encoded AVX instructions support 256-bit and 128-bit floating-point operations by extending the legacy 
128-bit SIMD floating-point instructions to support three-operand syntax. 
Additional functional enhancements are also provided with VEX-encoded AVX instructions.
The list of AVX instructions are listed in the following tables:

•

Table 14-2 lists 256-bit and 128-bit floating-point arithmetic instructions promoted from legacy 128-bit SIMD 
instruction sets.

•

Table 14-3 lists 256-bit and 128-bit data movement and processing instructions promoted from legacy 128-bit 
SIMD instruction sets.

•

Table 14-4 lists functional enhancements of 256-bit AVX instructions not available from legacy 128-bit SIMD 
instruction sets.

•

Table 14-5 lists 128-bit integer and floating-point instructions promoted from legacy 128-bit SIMD instruction 
sets.

•

Table 14-6 lists functional enhancements of 128-bit AVX instructions not available from legacy 128-bit SIMD 
instruction sets.

•

Table 14-7 lists 128-bit data movement and processing instructions promoted from legacy instruction sets.

5.14 16-BIT 

FLOATING-POINT 

CONVERSION

Conversion between single-precision floating-point (32-bit) and half-precision FP (16-bit) data are provided by 
VCVTPS2PH, VCVTPH2PS:
VCVTPH2PS

Convert eight/four data element containing 16-bit floating-point data into eight/four 

single-precision floating-point data.

VCVTPS2PH

Convert eight/four data element containing single-precision floating-point data into 

eight/four 16-bit floating-point data.