Vol. 1 5-9

INSTRUCTION SET SUMMARY

5.1.16.1   Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT, PREFETCHW

VEX-encoded general-purpose instructions do not operate on any vector registers. 
There are separate feature flags for the following subsets of instructions that operate on general purpose registers, 
and the detection requirements for hardware support are:
CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]: if 1 indicates the processor supports the first group of advanced bit 
manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT);
CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]: if 1 indicates the processor supports the second group of advanced 
bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX);
CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicates the processor supports the LZCNT instruction.
CPUID.EAX=80000001H:ECX.PREFTEHCHW[bit 8]: if 1 indicates the processor supports the PREFTEHCHW instruc-
tion. CPUID.(EAX=07H, ECX=0H):ECX.PREFTEHCHWT1[bit 0]: if 1 indicates the processor supports the 
PREFTEHCHWT1 instruction.

5.2 

X87 FPU INSTRUCTIONS

The x87 FPU instructions are executed by the processor’s x87 FPU. These instructions operate on floating-point, 
integer, and binary-coded decimal (BCD) operands. For more detail on x87 FPU instructions, see Chapter 8, 
“Programming with the x87 FPU.”
These instructions are divided into the following subgroups: data transfer, load constants, and FPU control instruc-
tions. The sections that follow introduce each subgroup.

5.2.1 

x87 FPU Data Transfer Instructions

The data transfer instructions move floating-point, integer, and BCD values between memory and the x87 FPU 
registers. They also perform conditional move operations on floating-point operands.
FLD

Load floating-point value.

FST

Store floating-point value.

FSTP

Store floating-point value and pop.

FILD

Load integer.

FIST

Store integer.

FISTP

1

Store integer and pop.

FBLD

Load BCD.

FBSTP

Store BCD and pop.

FXCH

Exchange registers.

FCMOVE

Floating-point conditional move if equal.

FCMOVNE

Floating-point conditional move if not equal.

FCMOVB

Floating-point conditional move if below.

FCMOVBE

Floating-point conditional move if below or equal.

FCMOVNB

Floating-point conditional move if not below.

FCMOVNBE

Floating-point conditional move if not below or equal.

FCMOVU

Floating-point conditional move if unordered.

FCMOVNU

Floating-point conditional move if not unordered.

5.2.2 

x87 FPU Basic Arithmetic Instructions

The basic arithmetic instructions perform basic arithmetic operations on floating-point and integer operands.

1. SSE3 provides an instruction FISTTP for integer conversion.