19-220 Vol. 3B

PERFORMANCE-MONITORING EVENTS

37H

MISPREDICTED_

OR_

UNPREDICTED_

RETURNS

(Counter 1)

Number of returns predicted 

incorrectly or not predicted at all

The count is the difference between the total number of 

executed returns and the number of returns that were 

correctly predicted. Only RET instructions are counted (for 

example, IRET instructions are not counted).

37H

PREDICTED_

RETURNS

(Counter 1)

Number of predicted returns (whether 

they are predicted correctly and 

incorrectly

Only RET instructions are counted (for example, IRET 

instructions are not counted).

38H

MMX_MULTIPLY_

UNIT_INTERLOCK 

(Counter 0)

Number of clocks the pipe is stalled 

since the destination of previous MMX 

multiply instruction is not ready yet

The counter will not be incremented if there is another 

cause for a stall. For each occurrence of a multiply 

interlock, this event will be counted twice (if the stalled 

instruction comes on the next clock after the multiply) or 

by once (if the stalled instruction comes two clocks after 

the multiply).

38H

MOVD/MOVQ_

STORE_STALL_

DUE_TO_

PREVIOUS_MMX_

OPERATION 

(Counter 1)

Number of clocks a MOVD/MOVQ 

instruction store is stalled in D2 stage 

due to a previous MMX operation with 

a destination to be used in the store 

instruction.

39H

RETURNS 

(Counter 0)

Number or returns executed. 

Only RET instructions are counted; IRET instructions are 

not counted. Any exception taken on a RET instruction 

and any interrupt recognized by the processor on the 

instruction boundary prior to the execution of the RET 

instruction will also cause this counter to be incremented.

39H

Reserved

3AH

BTB_FALSE_

ENTRIES 

(Counter 0)

Number of false entries in the Branch 

Target Buffer

False entries are causes for misprediction other than a 

wrong prediction.

3AH

BTB_MISS_

PREDICTION_ON_

NOT-TAKEN_

BRANCH 

(Counter 1)

Number of times the BTB predicted a 

not-taken branch as taken

3BH

FULL_WRITE_

BUFFER_STALL_

DURATION_

WHILE_

EXECUTING_MMX_I

NSTRUCTIONS 

(Counter 0)

Number of clocks while the pipeline is 

stalled due to full write buffers while 

executing MMX instructions

3BH

STALL_ON_MMX_

INSTRUCTION_

WRITE_TO E-_OR_

M-STATE_LINE 

(Counter 1)

Number of clocks during stalls on MMX 

instructions writing to E- or M-state 

lines

Table 19-38.  Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)

Event

Num.

Mnemonic Event 

Name

Description

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