19-212 Vol. 3B

PERFORMANCE-MONITORING EVENTS

Does not include stalls due to bus queue full, 

too many cache misses, etc.
In addition to resource related stalls, this 

event counts some other events.
Includes stalls arising during branch 

misprediction recovery, such as if retirement 

of the mispredicted branch is delayed and 

stalls arising while store buffer is draining 

from synchronizing operations.

D2H

PARTIAL_RAT_

STALLS

00H

Number of cycles or events for partial stalls. 

This includes flag partial stalls.

Segment 

Register 

Loads

06H

SEGMENT_REG_

LOADS

00H

Number of segment register loads.

Clocks

79H

CPU_CLK_

UNHALTED

00H

Number of cycles during which the 

processor is not halted.

MMX Unit

B0H

MMX_INSTR_

EXEC

00H

Number of MMX Instructions Executed.

Available in Intel Celeron, Pentium II 

and Pentium II Xeon processors 

only.
Does not account for MOVQ and 

MOVD stores from register to 

memory.

B1H

MMX_SAT_

INSTR_EXEC

00H

Number of MMX Saturating Instructions 

Executed.

Available in Pentium

 

II and Pentium

 

III processors only.

B2H

MMX_UOPS_

EXEC

0FH

Number of MMX μops Executed.

Available in Pentium

 

II and Pentium

 

III processors only.

B3H

MMX_INSTR_

TYPE_EXEC

01H

02H

04H

MMX packed multiply instructions executed.
MMX packed shift instructions executed.
MMX pack operation instructions executed.

Available in Pentium

 

II and Pentium

 

III processors only.

08H

10H

20H

MMX unpack operation instructions 

executed.
MMX packed logical instructions executed.
MMX packed arithmetic instructions 

executed.

CCH

FP_MMX_TRANS

00H

01H

Transitions from MMX instruction to 

floating-point instructions.
Transitions from floating-point instructions 

to MMX instructions.

Available in Pentium

 

II and Pentium

 

III processors only.

CDH

MMX_ASSIST

00H

Number of MMX Assists (that is, the number 

of EMMS instructions executed).

Available in Pentium

 

II and Pentium

 

III processors only.

CEH

MMX_INSTR_RET 00H

Number of MMX Instructions Retired.

Available in Pentium

 

II processors 

only.

Segment 

Register 

Renaming

D4H

SEG_RENAME_

STALLS

Number of Segment Register Renaming 

Stalls:

Available in Pentium

 

II and Pentium

 

III processors only.

Table 19-37.  Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)

Unit

Event 

Num.

Mnemonic Event 

Name

Unit 

Mask Description

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