19-190 Vol. 3B

PERFORMANCE-MONITORING EVENTS

CCCR Select

03H

CCCR[15:13]

Event Specific 

Notes

This event may not be supported in all models of the processor 

family.

bnr

This event can be configured to count bus not ready conditions using 

sub-event mask bits 0 through 2.

ESCR restrictions

MSR_FSB_ESCR0
MSR_FSB_ESCR1 

Counter numbers 

per ESCR

ESCR0: 0, 1 
ESCR1: 2, 3 

ESCR Event Select

08H

ESCR[30:25]

Event Masks

Bit 

ESCR[24:9]

CCCR Select

03H

CCCR[15:13]

Event Specific 

Notes

This event may not be supported in all models of the processor 

family.

snoop

This event can be configured to count snoop hit modified bus traffic 

using sub-event mask bits 2, 6 and 7.

ESCR restrictions

MSR_FSB_ESCR0 

MSR_FSB_ESCR1 

Counter numbers 

per ESCR

ESCR0: 0, 1 
ESCR1: 2, 3 

ESCR Event Select

06H

ESCR[30:25]

Event Masks

Bit 

ESCR[24:9]

CCCR Select

03H

CCCR[15:13]

Event Specific 

Notes

This event may not be supported in all models of the processor 

family.

Response

This event can be configured to count different types of responses 

using sub-event mask bits 1,2, 8, and 9.

ESCR restrictions

MSR_FSB_ESCR0
MSR_FSB_ESCR1 

Counter numbers 

per ESCR

ESCR0: 0, 1 
ESCR1: 2, 3 

ESCR Event Select

04H

ESCR[30:25]

Event Masks

Bit 

ESCR[24:9]

CCCR Select

03H

CCCR[15:13]

Event Specific 

Notes

This event may not be supported in all models of the processor 

family.

Table 19-28.  Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture 

for Non-Retirement Counting (Contd.)

Event Name

Event Parameters  Parameter Value

Description