Vol. 3B 19-189

PERFORMANCE-MONITORING EVENTS

Event Specific 

Notes

This event may overcount conditional branches if :
• Mispredictions cause the trace cache and delivery engine to build 

new traces.

• When the processor's pipeline is being cleared. 

resource_stall

This event monitors the occurrence or latency of stalls in the 

Allocator.

ESCR restrictions

MSR_ALF_ESCR0
MSR_ALF_ESCR1 

Counter numbers 

per ESCR

ESCR0: 12, 13, 16 

ESCR1: 14, 15, 17 

ESCR Event Select

01H

ESCR[30:25]

Event Masks

Bit

ESCR[24:9]

5: SBFULL 

A Stall due to lack of store buffers.

CCCR Select

01H

CCCR[15:13]

Event Specific 

Notes

This event may not be supported in all models of the processor 

family.

WC_Buffer

This event counts Write Combining Buffer operations that are 

selected by the event mask.

ESCR restrictions

MSR_DAC_ESCR0
MSR_DAC_ESCR1 

Counter numbers 

per ESCR

ESCR0: 8, 9 
ESCR1: 10, 11 

ESCR Event Select

05H 

ESCR[30:25]

Event Masks

Bit

ESCR[24:9]

0: WCB_EVICTS 

WC Buffer evictions of all causes.

1: WCB_FULL_

    EVICT

WC Buffer eviction: no WC buffer is available.

CCCR Select

05H

CCCR[15:13]

Event Specific 

Notes

This event is useful for detecting the subset of 64K aliasing cases 

that are more costly (i.e. 64K aliasing cases involving stores) as long 

as there are no significant contributions due to write combining 

buffer full or hit-modified conditions.

b2b_cycles

This event can be configured to count the number back-to-back bus 

cycles using sub-event mask bits 1 through 6.

ESCR restrictions

MSR_FSB_ESCR0
MSR_FSB_ESCR1 

Counter numbers 

per ESCR

ESCR0: 0, 1 
ESCR1: 2, 3 

ESCR Event Select

016H

ESCR[30:25]

Event Masks

Bit 

ESCR[24:9]

Table 19-28.  Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture 

for Non-Retirement Counting (Contd.)

Event Name

Event Parameters  Parameter Value

Description