19-188 Vol. 3B

PERFORMANCE-MONITORING EVENTS

ESCR Event Select

09H

ESCR[31:25]

ESCR Event Mask

Bit 
0: FROM_TC_

BUILD

ESCR[24:9]

The uops being written are from TC build mode.

1: FROM_TC_

DELIVER
2: FROM_ROM

The uops being written are from TC deliver mode.
The uops being written are from microcode ROM.

CCCR Select

0H

CCCR[15:13]

retired_mispred
_branch_type

This event counts retiring mispredicted branches by type.

ESCR restrictions

MSR_TBPU_ESCR0
MSR_TBPU_ESCR1 

Counter numbers 

per ESCR

ESCR0: 4, 5
ESCR1: 6, 7

ESCR Event Select

05H

ESCR[30:25]

ESCR Event Mask

Bit
1: CONDITIONAL
2: CALL

ESCR[24:9]

Conditional jumps.
Indirect call branches.

3: RETURN
4: INDIRECT

Return branches.
Returns, indirect calls, or indirect jumps.

CCCR Select

02H

CCCR[15:13]

Event Specific 

Notes

This event may overcount conditional branches if:
• Mispredictions cause the trace cache and delivery engine to build 

new traces.

• When the processor's pipeline is being cleared. 

retired_branch
_type

This event counts retiring branches by type. Specify one or more 

mask bits to qualify the branch by its type.

ESCR restrictions

MSR_TBPU_ESCR0
MSR_TBPU_ESCR1 

Counter numbers 

per ESCR

ESCR0: 4, 5
ESCR1: 6, 7

ESCR Event Select

04H 

ESCR[30:25]

ESCR Event Mask

Bit
1: CONDITIONAL
2: CALL

ESCR[24:9]

Conditional jumps.
Direct or indirect calls.

3: RETURN
4: INDIRECT

Return branches.
Returns, indirect calls, or indirect jumps.

CCCR Select

02H

CCCR[15:13]

Table 19-28.  Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture 

for Non-Retirement Counting (Contd.)

Event Name

Event Parameters  Parameter Value

Description