19-186 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Event Specific
Notes
If an instruction contains more than one scalar DP μops, each scalar
DP μop that is specified by the event mask is counted.
64bit_MMX_uop
This event increments for each MMX instruction, which operate on
64-bit SIMD operands.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR1: 10, 11
ESCR Event Select
02H
ESCR[31:25]
ESCR Event Mask
Bit 15: ALL
ESCR[24:9]
Count all μops operating on 64- bit SIMD integer operands in memory
or MMX registers.
CCCR Select
01H
CCCR[15:13]
Event Specific
Notes
If an instruction contains more than one 64-bit MMX μops, each 64-
bit MMX μop that is specified by the event mask will be counted.
128bit_MMX_uop
This event increments for each integer SIMD SSE2 instruction, which
operate on 128-bit SIMD operands.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR1: 10, 11
ESCR Event Select
1AH
ESCR[31:25]
ESCR Event Mask
Bit 15: ALL
ESCR[24:9]
Count all μops operating on 128-bit SIMD integer operands in
memory or XMM registers.
CCCR Select
01H
CCCR[15:13]
Event Specific
Notes
If an instruction contains more than one 128-bit MMX μops, each
128-bit MMX μop that is specified by the event mask will be counted.
x87_FP_uop
This event increments for each x87 floating-point μop, specified
through the event mask for detection.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR1: 10, 11
ESCR Event Select
04H
ESCR[31:25]
ESCR Event Mask
Bit 15: ALL
ESCR[24:9]
Count all x87 FP μops.
CCCR Select
01H
CCCR[15:13]
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters Parameter Value
Description