Vol. 3B 19-175
PERFORMANCE-MONITORING EVENTS
ESCR Event Mask
Bit 0: TCMISS
ESCR[24:9]
Trace cache lookup miss
CCCR Select
00H
CCCR[15:13]
ITLB_reference
This event counts translations using the Instruction Translation
Look-aside Buffer (ITLB).
ESCR restrictions
MSR_ITLB_ESCR0
MSR_ITLB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR1: 2, 3
ESCR Event Select
18H
ESCR[31:25]
ESCR Event Mask
Bit
0: HIT
1: MISS
2: HIT_UC
ESCR[24:9]
ITLB hit
ITLB miss
Uncacheable ITLB hit
CCCR Select
03H
CCCR[15:13]
Event Specific
Notes
All page references regardless of the page size are looked up as
actual 4-KByte pages. Use the page_walk_type event with the
ITMISS mask for a more conservative count.
memory_cancel
This event counts the canceling of various type of request in the
Data cache Address Control unit (DAC). Specify one or more mask
bits to select the type of requests that are canceled.
ESCR restrictions
MSR_DAC_ESCR0
MSR_DAC_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR1: 10, 11
ESCR Event Select
02H
ESCR[31:25]
ESCR Event Mask
Bit
2: ST_RB_FULL
3: 64K_CONF
ESCR[24:9]
Replayed because no store request buffer is available.
Conflicts due to 64-KByte aliasing.
CCCR Select
05H
CCCR[15:13]
Event Specific
Notes
All_CACHE_MISS includes uncacheable memory in count.
memory_
complete
This event counts the completion of a load split, store split,
uncacheable (UC) split, or UC load. Specify one or more mask bits to
select the operations to be counted.
ESCR restrictions
MSR_SAAT_ESCR0
MSR_SAAT_ESCR1
Table 19-28. Performance Monitoring Events Supported by Intel NetBurstĀ® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters Parameter Value
Description