Vol. 3B 19-169

PERFORMANCE-MONITORING EVENTS

26H

L2_Lines_Out

00H

L2 cache lines evicted.

Requires core-specificity 

and HW prefetch 

qualification.

27H

L2_M_Lines_Out

00H

L2 Modified-state cache lines evicted.

28H

L2_IFetch

Requires MESI 

qualification

L2 instruction fetches from instruction fetch unit 

(includes speculative fetches).

Requires core-

specificity.

29H

L2_LD

Requires MESI 

qualification

L2 cache reads.

Requires core-

specificity.

2AH

L2_ST

Requires MESI 

qualification

L2 cache writes (includes speculation).

Requires core-

specificity.

2EH

L2_Rqsts

Requires MESI 

qualification

L2 cache reference requests.

Requires core-

specificity, HW prefetch 

qualification.

30H

L2_Reject_Cycles

Requires MESI 

qualification

Cycles L2 is busy and rejecting new requests.

32H

L2_No_Request_

Cycles

Requires MESI 

qualification

Cycles there is no request to access L2.

3AH

EST_Trans_All

00H

Any Intel Enhanced SpeedStep(R) Technology 

transitions.

3AH

EST_Trans_All

10H

Intel Enhanced SpeedStep Technology frequency 

transitions.

3BH

Thermal_Trip

C0H

Duration in a thermal trip based on the current core 

clock.

Use edge trigger to 

count occurrence.

3CH

NonHlt_Ref_Cycles

01H

Non-halted bus cycles.

3CH

Serial_Execution_

Cycles

02H

Non-halted bus cycles of this core executing code 

while the other core is halted.

40H

DCache_Cache_LD

Requires MESI 

qualification

L1 cacheable data read operations.

41H

DCache_Cache_ST

Requires MESI 

qualification

L1 cacheable data write operations.

42H

DCache_Cache_

Lock

Requires MESI 

qualification

L1 cacheable lock read operations to invalid state.

43H

Data_Mem_Ref

01H

L1 data read and writes of cacheable and non-

cacheable types.

44H

Data_Mem_Cache_

Ref

02H

L1 data cacheable read and write operations.

45H

DCache_Repl

0FH

L1 data cache line replacements.

46H

DCache_M_Repl

00H

L1 data M-state cache line allocated.

47H

DCache_M_Evict

00H

L1 data M-state cache line evicted.

48H

DCache_Pend_Miss

00H

Weighted cycles of L1 miss outstanding.

Use Cmask =1 to count 

duration.

49H

Dtlb_Miss

00H

Data references that missed TLB.

4BH

SSE_PrefNta_Miss

00H

PREFETCHNTA missed all caches.

4BH

SSE_PrefT1_Miss

01H

PREFETCHT1 missed all caches.

4BH

SSE_PrefT2_Miss

02H

PREFETCHT2 missed all caches.

4BH

SSE_NTStores_

Miss

03H

SSE streaming store instruction missed all caches.

Table 19-27.  Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors (Contd.)

Event

Num.

Event Mask 

Mnemonic

Umask

Value

Description

Comment