Vol. 3B 19-139

PERFORMANCE-MONITORING EVENTS

CBH

08H

MEM_LOAD_

RETIRED.L2_LINE_MISS

L2 cache line missed 

by retired loads 

(precise event).

This event counts the number of load operations that miss 

the L2 cache and result in a bus request to fetch the missing 

cache line. That is the missing cache line fetching has not 

yet started.
This event count is equal to the number of cache lines 

fetched from memory by retired loads. 
This event counts loads from cacheable memory only. The 

event does not count loads by software prefetches. 
The event might not be counted if the load is blocked (see 

LOAD_BLOCK events).
When this event is captured with the precise event 

mechanism, the collected samples contain the address of 

the instruction that was executed immediately after the 

instruction that caused the event.
Use IA32_PMC0 only.

CBH

10H

MEM_LOAD_

RETIRED.DTLB_

MISS

Retired loads that miss 

the DTLB (precise 

event).

This event counts the number of retired loads that missed 

the DTLB. The DTLB miss is not counted if the load 

operation causes a fault.
This event counts loads from cacheable memory only. The 

event does not count loads by software prefetches. 
When this event is captured with the precise event 

mechanism, the collected samples contain the address of 

the instruction that was executed immediately after the 

instruction that caused the event. 
Use IA32_PMC0 only.

CCH

01H

FP_MMX_TRANS_TO_MMX Transitions from 

Floating Point to MMX 

Instructions.

This event counts the first MMX instructions following a 

floating-point instruction. Use this event to estimate the 

penalties for the transitions between floating-point and 

MMX states.

CCH

02H

FP_MMX_TRANS_TO_FP

Transitions from MMX 

Instructions to 

Floating Point 

Instructions.

This event counts the first floating-point instructions 

following any MMX instruction. Use this event to estimate 

the penalties for the transitions between floating-point and 

MMX states.

CDH

00H

SIMD_ASSIST

SIMD assists invoked.

This event counts the number of SIMD assists invoked. SIMD 

assists are invoked when an EMMS instruction is executed, 

changing the MMX state in the floating point stack.

CEH

00H

SIMD_INSTR_

RETIRED

SIMD Instructions 

retired.

This event counts the number of retired SIMD instructions 

that use MMX registers.

CFH

00H

SIMD_SAT_INSTR_RETIRED Saturated arithmetic 

instructions retired.

This event counts the number of saturated arithmetic SIMD 

instructions that retired.

D2H

01H

RAT_STALLS.

ROB_READ_PORT

ROB read port stalls 

cycles.

This event counts the number of cycles when ROB read port 

stalls occurred, which did not allow new micro-ops to enter 

the out-of-order pipeline. 
Note that, at this stage in the pipeline, additional stalls may 

occur at the same cycle and prevent the stalled micro-ops 

from entering the pipe. In such a case, micro-ops retry 

entering the execution pipe in the next cycle and the ROB-

read-port stall is counted again.

Table 19-23.  Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Event 

Num

Umask

Value

Event Name 

Definition

Description and

Comment