Vol. 3B 19-107

PERFORMANCE-MONITORING EVENTS

22H

02H

UNC_QHL_CYCLES_NOT_EMPT

Y.REMOTE

Counts uclk cycles all entries in the Quickpath Home 

Logic remote tracker is busy.

22H

04H

UNC_QHL_CYCLES_NOT_EMPT

Y.LOCAL

Counts uclk cycles all entries in the Quickpath Home 

Logic local tracker is busy.

23H

01H

UNC_QHL_OCCUPANCY.IOH

QHL IOH tracker allocate to deallocate read occupancy.

23H

02H

UNC_QHL_OCCUPANCY.REMOT

E

QHL remote tracker allocate to deallocate read 

occupancy.

23H

04H

UNC_QHL_OCCUPANCY.LOCAL QHL local tracker allocate to deallocate read 

occupancy.

24H

02H

UNC_QHL_ADDRESS_CONFLIC

TS.2WAY

Counts number of QHL Active Address Table (AAT) 

entries that saw a max of 2 conflicts. The AAT is a 

structure that tracks requests that are in conflict. The 

requests themselves are in the home tracker entries. 

The count is reported when an AAT entry deallocates.

24H

04H

UNC_QHL_ADDRESS_CONFLIC

TS.3WAY

Counts number of QHL Active Address Table (AAT) 

entries that saw a max of 3 conflicts. The AAT is a 

structure that tracks requests that are in conflict. The 

requests themselves are in the home tracker entries. 

The count is reported when an AAT entry deallocates.

25H

01H

UNC_QHL_CONFLICT_CYCLES.I

OH

Counts cycles the Quickpath Home Logic IOH Tracker 

contains two or more requests with an address 

conflict. A max of 3 requests can be in conflict.

25H

02H

UNC_QHL_CONFLICT_CYCLES.

REMOTE

Counts cycles the Quickpath Home Logic Remote 

Tracker contains two or more requests with an 

address conflict. A max of 3 requests can be in conflict.

25H

04H

UNC_QHL_CONFLICT_CYCLES.L

OCAL

Counts cycles the Quickpath Home Logic Local Tracker 

contains two or more requests with an address 

conflict. A max of 3 requests can be in conflict.

26H

01H

UNC_QHL_TO_QMC_BYPASS

Counts number or requests to the Quickpath Memory 

Controller that bypass the Quickpath Home Logic. All 

local accesses can be bypassed. For remote requests, 

only read requests can be bypassed.

28H

01H

UNC_QMC_ISOC_FULL.READ.C

H0

Counts cycles all the entries in the DRAM channel 0 

high priority queue are occupied with isochronous read 

requests.

28H

02H

UNC_QMC_ISOC_FULL.READ.C

H1

Counts cycles all the entries in the DRAM channel 

1high priority queue are occupied with isochronous 

read requests.

28H

04H

UNC_QMC_ISOC_FULL.READ.C

H2

Counts cycles all the entries in the DRAM channel 2 

high priority queue are occupied with isochronous read 

requests.

28H

08H

UNC_QMC_ISOC_FULL.WRITE.C

H0

Counts cycles all the entries in the DRAM channel 0 

high priority queue are occupied with isochronous 

write requests.

28H

10H

UNC_QMC_ISOC_FULL.WRITE.C

H1

Counts cycles all the entries in the DRAM channel 1 

high priority queue are occupied with isochronous 

write requests.

Table 19-20.  Non-Architectural Performance Events In the Processor Uncore for 

Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment