Vol. 3B 19-103
PERFORMANCE-MONITORING EVENTS
03H
02H
UNC_GQ_ALLOC.RT_L3_MISS
Counts the number GQ read tracker entries for which a
full cache line read has missed the L3. The GQ read
tracker L3 miss to fill occupancy count is divided by
this count to obtain the average cache line read L3
miss latency. The latency represents the time after
which the L3 has determined that the cache line has
missed. The time between a GQ read tracker allocation
and the L3 determining that the cache line has missed
is the average L3 hit latency. The total L3 cache line
read miss latency is the hit latency + L3 miss latency.
03H
04H
UNC_GQ_ALLOC.RT_TO_L3_RE
SP
Counts the number of GQ read tracker entries that are
allocated in the read tracker queue that hit or miss the
L3. The GQ read tracker L3 hit occupancy count is
divided by this count to obtain the average L3 hit
latency.
03H
08H
UNC_GQ_ALLOC.RT_TO_RTID_
ACQUIRED
Counts the number of GQ read tracker entries that are
allocated in the read tracker, have missed in the L3 and
have not acquired a Request Transaction ID. The GQ
read tracker L3 miss to RTID acquired occupancy count
is divided by this count to obtain the average latency
for a read L3 miss to acquire an RTID.
03H
10H
UNC_GQ_ALLOC.WT_TO_RTID_
ACQUIRED
Counts the number of GQ write tracker entries that are
allocated in the write tracker, have missed in the L3
and have not acquired a Request Transaction ID. The
GQ write tracker L3 miss to RTID occupancy count is
divided by this count to obtain the average latency for
a write L3 miss to acquire an RTID.
03H
20H
UNC_GQ_ALLOC.WRITE_TRAC
KER
Counts the number of GQ write tracker entries that are
allocated in the write tracker queue that miss the L3.
The GQ write tracker occupancy count is divided by
this count to obtain the average L3 write miss latency.
03H
40H
UNC_GQ_ALLOC.PEER_PROBE
_TRACKER
Counts the number of GQ peer probe tracker (snoop)
entries that are allocated in the peer probe tracker
queue that miss the L3. The GQ peer probe occupancy
count is divided by this count to obtain the average L3
peer probe miss latency.
04H
01H
UNC_GQ_DATA.FROM_QPI
Cycles Global Queue Quickpath Interface input data
port is busy importing data from the Quickpath
Interface. Each cycle the input port can transfer 8 or
16 bytes of data.
04H
02H
UNC_GQ_DATA.FROM_QMC
Cycles Global Queue Quickpath Memory Interface input
data port is busy importing data from the Quickpath
Memory Interface. Each cycle the input port can
transfer 8 or 16 bytes of data.
04H
04H
UNC_GQ_DATA.FROM_L3
Cycles GQ L3 input data port is busy importing data
from the Last Level Cache. Each cycle the input port
can transfer 32 bytes of data.
04H
08H
UNC_GQ_DATA.FROM_CORES_
02
Cycles GQ Core 0 and 2 input data port is busy
importing data from processor cores 0 and 2. Each
cycle the input port can transfer 32 bytes of data.
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on IntelĀ® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment