19-96 Vol. 3B

PERFORMANCE-MONITORING EVENTS

B0H

10H

OFFCORE_REQUESTS.ANY.RFO Counts number of offcore RFO requests. Includes L2 

prefetch requests.

B0H

40H

OFFCORE_REQUESTS.L1D_WR

ITEBACK

Counts number of L1D writebacks to the uncore. 

B0H

80H

OFFCORE_REQUESTS.ANY

Counts all offcore requests.

B1H

01H

UOPS_EXECUTED.PORT0

Counts number of uops executed that were issued 

on port 0. Port 0 handles integer arithmetic, SIMD 

and FP add uops.

B1H

02H

UOPS_EXECUTED.PORT1

Counts number of uops executed that were issued 

on port 1. Port 1 handles integer arithmetic, SIMD, 

integer shift, FP multiply and FP divide uops.

B1H

04H

UOPS_EXECUTED.PORT2_COR

E

Counts number of uops executed that were issued 

on port 2. Port 2 handles the load uops. This is a 

core count only and cannot be collected per thread.

B1H

08H

UOPS_EXECUTED.PORT3_COR

E

Counts number of uops executed that were issued 

on port 3. Port 3 handles store uops. This is a core 

count only and cannot be collected per thread.

B1H

10H

UOPS_EXECUTED.PORT4_COR

E

Counts number of uops executed that where issued 

on port 4. Port 4 handles the value to be stored for 

the store uops issued on port 3. This is a core count 

only and cannot be collected per thread.

B1H

1FH

UOPS_EXECUTED.CORE_ACTI

VE_CYCLES_NO_PORT5

Counts number of cycles there are one or more 

uops being executed and were issued on ports 0-4. 

This is a core count only and cannot be collected per 

thread.

B1H

20H

UOPS_EXECUTED.PORT5

Counts number of uops executed that where issued 

on port 5. 

B1H

3FH

UOPS_EXECUTED.CORE_ACTI

VE_CYCLES

Counts number of cycles there are one or more 

uops being executed on any ports. This is a core 

count only and cannot be collected per thread.

B1H

40H

UOPS_EXECUTED.PORT015

Counts number of uops executed that where issued 

on port 0, 1, or 5.

Use cmask=1, invert=1 

to count stall cycles.

B1H

80H

UOPS_EXECUTED.PORT234

Counts number of uops executed that where issued 

on port 2, 3, or 4.

B2H

01H

OFFCORE_REQUESTS_SQ_FUL

L

Counts number of cycles the SQ is full to handle off-

core requests. 

B3H

01H

SNOOPQ_REQUESTS_OUTSTA

NDING.DATA

Counts weighted cycles of snoopq requests for 

data. Counter 0 only.

Use cmask=1 to count 

cycles not empty. 

B3H

02H

SNOOPQ_REQUESTS_OUTSTA

NDING.INVALIDATE

Counts weighted cycles of snoopq invalidate 

requests. Counter 0 only.

Use cmask=1 to count 

cycles not empty. 

B3H

04H

SNOOPQ_REQUESTS_OUTSTA

NDING.CODE

Counts weighted cycles of snoopq requests for 

code. Counter 0 only.

Use cmask=1 to count 

cycles not empty. 

B4H

01H

SNOOPQ_REQUESTS.CODE

Counts the number of snoop code requests.

B4H

02H

SNOOPQ_REQUESTS.DATA

Counts the number of snoop data requests.

B4H

04H

SNOOPQ_REQUESTS.INVALID

ATE

Counts the number of snoop invalidate requests.

Table 19-19.  Non-Architectural Performance Events In the Processor Core for 

Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment