19-38 Vol. 3B
PERFORMANCE-MONITORING EVENTS
88H
40H
BR_INST_EXEC.NONTAKEN
Qualify non-taken near branches executed.
Applicable to umask 01H
only.
88H
80H
BR_INST_EXEC.TAKEN
Qualify taken near branches executed. Must
combine with 01H,02H, 04H, 08H, 10H, 20H.
88H
FFH
BR_INST_EXEC.ALL_BRANCHES
Counts all near executed branches (not necessarily
retired).
89H
01H
BR_MISP_EXEC.COND
Qualify conditional near branch instructions
mispredicted.
Must combine with
umask 40H, 80H.
89H
04H
BR_MISP_EXEC.INDIRECT_JMP_N
ON_CALL_RET
Qualify mispredicted indirect near branch
instructions that are not calls or returns.
Must combine with
umask 80H.
89H
08H
BR_MISP_EXEC.RETURN_NEAR
Qualify mispredicted indirect near branches that
have a return mnemonic.
Must combine with
umask 80H.
89H
10H
BR_MISP_EXEC.DIRECT_NEAR_C
ALL
Qualify mispredicted unconditional near call branch
instructions, excluding non-call branch, executed.
Must combine with
umask 80H.
89H
20H
BR_MISP_EXEC.INDIRECT_NEAR_
CALL
Qualify mispredicted indirect near calls, including
both register and memory indirect, executed.
Must combine with
umask 80H.
89H
40H
BR_MISP_EXEC.NONTAKEN
Qualify mispredicted non-taken near branches
executed.
Applicable to umask 01H
only.
89H
80H
BR_MISP_EXEC.TAKEN
Qualify mispredicted taken near branches executed.
Must combine with 01H,02H, 04H, 08H, 10H, 20H.
89H
FFH
BR_MISP_EXEC.ALL_BRANCHES
Counts all near executed branches (not necessarily
retired).
9CH
01H
IDQ_UOPS_NOT_DELIVERED.COR
E
Count issue pipeline slots where no uop was
delivered from the front end to the back end when
there is no back-end stall.
Use Cmask to qualify uop
b/w.
A1H
01H
UOPS_DISPATCHED_PORT.PORT_
0
Cycles which a Uop is dispatched on port 0.
A1H
02H
UOPS_DISPATCHED_PORT.PORT_
1
Cycles which a Uop is dispatched on port 1.
A1H
0CH
UOPS_DISPATCHED_PORT.PORT_
2
Cycles which a Uop is dispatched on port 2.
A1H
30H
UOPS_DISPATCHED_PORT.PORT_
3
Cycles which a Uop is dispatched on port 3.
A1H
40H
UOPS_DISPATCHED_PORT.PORT_
4
Cycles which a Uop is dispatched on port 4.
A1H
80H
UOPS_DISPATCHED_PORT.PORT_
5
Cycles which a Uop is dispatched on port 5.
A2H
01H
RESOURCE_STALLS.ANY
Cycles Allocation is stalled due to Resource Related
reason.
A2H
04H
RESOURCE_STALLS.RS
Cycles stalled due to no eligible RS entry available.
A2H
08H
RESOURCE_STALLS.SB
Cycles stalled due to no store buffers available (not
including draining form sync).
A2H
10H
RESOURCE_STALLS.ROB
Cycles stalled due to re-order buffer full.
A3H
01H
CYCLE_ACTIVITY.CYCLES_L2_PEN
DING
Cycles with pending L2 miss loads. Set AnyThread
to count per core.
Table 19-11. Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment