19-6 Vol. 3B

PERFORMANCE-MONITORING EVENTS

60H

02H

OFFCORE_REQUESTS_OUTSTAN

DING.DEMAND_CODE_RD

Increment each cycle of the number of offcore 

outstanding demand code read transactions in SQ to 

uncore. 

60H

02H

OFFCORE_REQUESTS_OUTSTAN

DING.CYCLES_WITH_DEMAND_C

ODE_RD

Cycles with at least one offcore outstanding demand 

code read transactions in SQ to uncore. 

CMSK1

60H

04H

OFFCORE_REQUESTS_OUTSTAN

DING.DEMAND_RFO

Increment each cycle of the number of offcore 

outstanding RFO store transactions in SQ to uncore. Set 

Cmask=1 to count cycles.

60H

04H

OFFCORE_REQUESTS_OUTSTAN

DING.CYCLES_WITH_DEMAND_R

FO

Cycles with at least one offcore outstanding RFO 

transactions in SQ to uncore. 

CMSK1

60H

08H

OFFCORE_REQUESTS_OUTSTAN

DING.ALL_DATA_RD

Increment each cycle of the number of offcore 

outstanding cacheable data read transactions in SQ to 

uncore. Set Cmask=1 to count cycles.

60H

08H

OFFCORE_REQUESTS_OUTSTAN

DING.CYCLES_WITH_DATA_RD

Cycles with at least one offcore outstanding data read 

transactions in SQ to uncore. 

CMSK1

60H

10H

OFFCORE_REQUESTS_OUTSTAN

DING.L3_MISS_DEMAND_DATA_

RD

Increment each cycle of the number of offcore 

outstanding demand data read requests from SQ that 

missed L3. 

60H

10H

OFFCORE_REQUESTS_OUTSTAN

DING.CYCLES_WITH_L3_MISS_D

EMAND_DATA_RD

Cycles with at least one offcore outstanding demand 

data read requests from SQ that missed L3. 

CMSK1

60H

10H

OFFCORE_REQUESTS_OUTSTAN

DING.L3_MISS_DEMAND_DATA_

RD_GE_6

Cycles with at least one offcore outstanding demand 

data read requests from SQ that missed L3. 

CMSK6

63H

02H

LOCK_CYCLES.CACHE_LOCK_DU

RATION

Cycles in which the L1D is locked.

79H

04H

IDQ.MITE_UOPS

Increment each cycle # of uops delivered to IDQ from 

MITE path. 

79H

04H

IDQ.MITE_CYCLES

Cycles when uops are being delivered to IDQ from MITE 

path.

CMSK1

79H

08H

IDQ.DSB_UOPS

Increment each cycle. # of uops delivered to IDQ from 

DSB path. 

79H

08H

IDQ.DSB_CYCLES

Cycles when uops are being delivered to IDQ from DSB 

path.

CMSK1

79H

10H

IDQ.MS_DSB_UOPS

Increment each cycle # of uops delivered to IDQ by DSB 

when MS_busy. 

79H

18H

IDQ.ALL_DSB_CYCLES_ANY_UO

PS

Cycles DSB is delivered at least one uops. 

CMSK1

79H

18H

IDQ.ALL_DSB_CYCLES_4_UOPS

Cycles DSB is delivered four uops. 

CMSK4

79H

20H

IDQ.MS_MITE_UOPS

Increment each cycle # of uops delivered to IDQ by 

MITE when MS_busy. 

79H

24H

IDQ.ALL_MITE_CYCLES_ANY_UO

PS

Counts cycles MITE is delivered at least one uops. 

CMSK1

79H

24H

IDQ.ALL_MITE_CYCLES_4_UOPS Counts cycles MITE is delivered four uops. 

CMSK4

79H

30H

IDQ.MS_UOPS

Increment each cycle # of uops delivered to IDQ while 

MS is busy. 

Table 19-3.  Non-Architectural Performance Events of the Processor Core Supported by Skylake Microarchitecture

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment