16-32 Vol. 3B

INTERPRETING MACHINE-CHECK ERROR CODES

All errors - except for the correctable ECC types - in this table are uncorrectable. The correctable ECC events may 
supply the ECC syndrome in the Other_Info field of the MC4_STATUS MSR.

Table 16-38.  Decoding Family 0FH Machine Check Codes for Cache Hierarchy Errors

Type

Bit No.  Bit Function

Bit Description

MCA error 

codes

1

NOTES:

1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.

0-15

Model 

specific error 

codes

16-17

Tag Error Code

Contains the tag error code for this machine check error:
00 = No error detected
01 = Parity error on tag miss with a clean line
10 = Parity error/multiple tag match on tag hit
11 = Parity error/multiple tag match on tag miss

18-19

Data Error Code

Contains the data error code for this machine check error:
00 = No error detected
01 = Single bit error
10 = Double bit error on a clean line
11 = Double bit error on a modified line

20

L3 Error

This bit is set if the machine check error originated in the L3 it can be ignored for 

invalid PIC request errors):
1 = L3 error
0 = L2 error

21

Invalid PIC Request

Indicates error due to invalid PIC request access was made to PIC space with WB 

memory):
1 = Invalid PIC request error
0 = No invalid PIC request error

22-31

Reserved

Reserved

Other 

Information

32-39

8-bit Error Count

Holds a count of the number of errors since reset. The counter begins at 0 for the 

first error and saturates at a count of 255.

40-56

Reserved

Reserved

Status 

register 

validity 

indicators

1

57-63