16-18 Vol. 3B

INTERPRETING MACHINE-CHECK ERROR CODES

Table 16-22.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16)

Table 16-23.  Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9-16)

Type

Bit No.  Bit Function 

Bit Description

MCA error codes

1

 

NOTES:

1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.

0-15

MCACOD

Memory Controller error format: 0000 0000 1MMM CCCC

Model specific 

errors

31:16

Reserved except for 

the following

0001H - DDR3 address parity error
0002H - Uncorrected HA write data error
0004H - Uncorrected HA data byte enable error
0008H - Corrected patrol scrub error
0010H - Uncorrected patrol scrub error
0020H - Corrected spare error
0040H - Uncorrected spare error
0080H - Corrected memory read error. (Only applicable with iMC’s “Additional 

Error logging” Mode-1 enabled.) 
0100H - iMC, write data buffer parity errors
0200H - DDR4 command address parity error

36-32

Other info

When MSR_ERROR_CONTROL.[1] is set,

 logs an encoded value from the first error 

device.

37

Reserved

Reserved

56-38

See Chapter 15, “Machine-Check Architecture,”

Status register 

validity indicators

1

 

57-63

Type

Bit No.  Bit Function 

Bit Description

MCA addr info

1

  0-8

See Chapter 15, “Machine-Check Architecture,”

Model specific 

errors

13:9

If the error logged is MCWrDataPar error or MCWrBEPar error, this field is the WDB 

ID that has the parity error. OR if the second error logged is a correctable read 

error, MC logs the second error device in this field.

Model specific 

errors

29-14

ErrMask_1stErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error bit 

mask.

Model specific 

errors

45-30

ErrMask_2ndErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error 

bit mask.

50:46

FailRank_1stErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error 

failing rank.

55:51

FailRank_2ndErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error 

failing rank.

61:56

Reserved

62

Valid_1stErrDev

When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data 

from a correctable error from memory read associated with first error device.

63

Valid_2ndErrDev

When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data due 

to a second correctable error in a memory device. Use this information only after 

there is valid first error info indicated by bit 62.