16-12 Vol. 3B

INTERPRETING MACHINE-CHECK ERROR CODES

tion logging of the IMC. The additional error information logged by the IMC is stored in IA32_MCi_STATUS and 
IA32_MCi_MISC; (i = 8, 11).

Table 16-15.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 8, 11)

Table 16-16.  Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11)

Type

Bit No.  Bit Function 

Bit Description

MCA error codes

1

 

NOTES:

1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.

0-15

MCACOD

Bus error format: 1PPTRRRRIILL

Model specific 

errors

31:16

Reserved except for 

the following

001H - Address parity error
002H - HA Wrt buffer Data parity error
004H - HA Wrt byte enable parity error
008H - Corrected patrol scrub error
010H - Uncorrected patrol scrub error
020H - Corrected spare error
040H - Uncorrected spare error

Model specific 

errors

36-32

Other info

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first device 

error when corrected error is detected during normal read.

37

Reserved

Reserved

56-38

See Chapter 15, “Machine-Check Architecture,”

Status register 

validity  indicators

1

 

57-63

Type

Bit No.  Bit Function 

Bit Description

MCA addr info

1

 

NOTES:

1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.

0-8

See Chapter 15, “Machine-Check Architecture,”

Model specific 

errors

13:9

• When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second device 

error when corrected error is detected during normal read.

• Otherwise contain parity error if MCi_Status indicates HA_WB_Data or 

HA_W_BE parity error.

Model specific 

errors

29-14

ErrMask_1stErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error bit 

mask.

Model specific 

errors

45-30

ErrMask_2ndErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error 

bit mask.

50:46

FailRank_1stErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error 

failing rank.

55:51

FailRank_2ndErrDev

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error 

failing rank.

58:56

Reserved

Reserved

61-59

Reserved

Reserved

62

Valid_1stErrDev

When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data 

from the first correctable error in a memory device.

63

Valid_2ndErrDev

When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data due 

to a second correctable error in a memory device. Use this information only after 

there is valid first error info indicated by bit 62.