Vol. 3A 11-3

MEMORY CACHE CONTROL

L2 Unified Cache

• Intel Core 2 Duo and Intel Xeon processors: up to 4-MByte (or 4MBx2 in quadcore processors), 16-way set 

associative, 64-byte cache line size.

• Intel Core 2 Duo and Intel Xeon processors: up to 6-MByte (or 6MBx2 in quadcore processors), 24-way set 

associative, 64-byte cache line size.

• Intel Core i7, i5, i3 processors: 256KBbyte, 8-way set associative, 64-byte cache line size.

• Intel Atom processors: 512-KByte, 8-way set associative, 64-byte cache line size.

• Intel Core Duo, Intel Core Solo processors: 2-MByte, 8-way set associative, 64-byte cache line size 

• Pentium 4 and Intel Xeon processors: 256, 512, 1024, or 2048-KByte, 8-way set associative, 64-byte cache 

line size, 128-byte sector size.

• Pentium M processor: 1 or 2-MByte, 8-way set associative, 64-byte cache line size.

• P6 family processors: 128-KByte, 256-KByte, 512-KByte, 1-MByte, or 2-MByte, 4-way set associative, 

32-byte cache line size.

• Pentium processor (external optional): System specific, typically 256- or 512-KByte, 4-way set associative, 

32-byte cache line size.

L3 Unified Cache

• Intel Xeon processors: 512-KByte, 1-MByte, 2-MByte, or 4-MByte, 8-way set associative, 64-byte cache line 

size, 128-byte sector size.

• Intel Core i7 processor, Intel Xeon processor 5500: Up to 8MByte, 16-way set associative, 64-byte cache 

line size.

• Intel Xeon processor 5600: Up to 12MByte, 64-byte cache line size.

• Intel Xeon processor 7500: Up to 24MByte, 64-byte cache line size.

Instruction TLB

(4-KByte Pages)

• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 128 entries, 4-way set 

associative.

• Intel Atom processors: 32-entries, fully associative.

• Intel Core i7, i5, i3 processors: 64-entries per thread (128-entries per core), 4-way set associative.

• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set 

associative.

• P6 family processors: 32 entries, 4-way set associative.

• Pentium processor: 32 entries, 4-way set associative; fully set associative for Pentium processors with MMX 

technology.

Data TLB (4-KByte 

Pages)

• Intel Core i7, i5, i3 processors, DTLB0: 64-entries, 4-way set associative.

• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 256 entries, 4 ways.

• Intel Atom processors: 16-entry-per-thread micro-TLB, fully associative; 64-entry DTLB, 4-way set 

associative; 16-entry PDE cache, fully associative.

• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 64 entry, fully set 

associative, shared with large page DTLB.

• Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set associative.

• Pentium and P6 family processors: 64 entries, 4-way set associative; fully set, associative for Pentium 

processors with MMX technology.

Instruction TLB 

(Large Pages)

• Intel Core i7, i5, i3 processors: 7-entries per thread, fully associative.

• Intel Core 2 Duo processors: 4 entries, 4 ways.

• Pentium 4 and Intel Xeon processors: large pages are fragmented.

• Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entries, fully associative.

• P6 family processors: 2 entries, fully associative.

• Pentium processor: Uses same TLB as used for 4-KByte pages.

Data TLB (Large 

Pages)

• Intel Core i7, i5, i3 processors, DTLB0: 32-entries, 4-way set associative.

• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 32 entries, 4 ways.

• Intel Atom processors: 8 entries, 4-way set associative.

• Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared with small page data TLBs.

• Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entries, fully associative.

• P6 family processors: 8 entries, 4-way set associative.

• Pentium processor: 8 entries, 4-way set associative; uses same TLB as used for 4-KByte pages in Pentium 

processors with MMX technology.

Second-level Unified 

TLB (4-KByte 

Pages)

• Intel Core i7, i5, i3 processor, STLB: 512-entries, 4-way set associative.

Table 11-1.  Characteristics of the Caches, TLBs, Store Buffer, and 

Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)

Cache or Buffer

Characteristics