36-68 Vol. 3C

INTEL® PROCESSOR TRACE

10d

Far Branch (CALL/JMP/RET)

1

0

1

*PIP if CR3 is updated (i.e.,

task switch), and OS=1;

*PIP.NR=1 if destination is 

not root operation, and 

“Conceal VMX non-root 

operation from Intel PT” 

execution control = 0;

*TraceStop if BLIP is in a 

TraceStop region

PIP(new CR3, NR?), 

TIP.PGD(BLIP), TraceStop?

10e

Far Branch (CALL/JMP/RET)

1

1

1

*PIP if CR3 is updated (i.e., 

task switch), and OS=1

*PIP.NR=1 if destination is 

not root operation, and 

“Conceal VMX non-root 

operation from Intel PT” 

execution control = 0;

* MODE.Exec if the opera-

tion changes CS.L/D or 

IA32_EFER.LMA 

PIP(NewCR3, NR?)?, 

MODE.Exec?, TIP(BLIP)

11a

HW Interrupt

0

0

0

None

11f

HW Interrupt

0

0

1

*PIP if CR3 is updated (i.e.,

task switch), and OS=1;

*PIP.NR=1 if destination is 

not root operation, and 

“Conceal VMX non-root 

operation from Intel PT” 

execution control = 0;

*TraceStop if BLIP is in a 

TraceStop region

PIP(new CR3, NR?), Trace-

Stop?

11b

HW Interrupt

0

1

1

*PIP if CR3 is updated (i.e.,

task switch), and OS=1;

*PIP.NR=1 if destination is 

not root operation, and 

“Conceal VMX non-root 

operation from Intel PT” 

execution control = 0;

* MODE.Exec if the mode 

has changed since the last 

MODE.Exec, or if no 

MODE.Exec since last PSB 

PIP(new CR3, NR?), 

MODE.Exec?, 

TIP.PGE(BLIP)

11c

HW Interrupt

1

0

0

FUP(NLIP), TIP.PGD()

11d

HW Interrupt

1

0

1

* PIP if CR3 is updated (i.e., 

task switch), and OS=1

*PIP.NR=1 if destination is 

not root operation, and 

“Conceal VMX non-root 

operation from Intel PT” 

execution control = 0;

*TraceStop if BLIP is in a 

TraceStop region

FUP(NLIP), PIP(NewCR3, 

NR?)?, TIP.PGD(BLIP), 

TraceStop

Table 36-50. Packet Generation under Different Enable Conditions (Contd.)

Case

Operation

PktEn 

Before

PktEn 

After

CntxEn 

After

Other Dependencies

Packets Output