Vol. 3C 35-325

MODEL-SPECIFIC REGISTERS (MSRS)

20

INT
Enables the signaling of counter overflow via input to APIC
1 = Enable
0 = Disable

22

ENABLE
Enables the counting of performance events in both counters
1 = Enable
0 = Disable

23

INV
Inverts the result of the CMASK condition
1 = Inverted
0 = Non-Inverted

31:24

CMASK (Counter Mask).

187H

391

PerfEvtSel1 (EVNTSEL1)
7:0

Event Select
Refer to Performance Counter section for a list of event encodings.

15:8

UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.

16

USER
Controls the counting of events at Privilege levels of 1, 2, and 3.

17

OS
Controls the counting of events at Privilege level of 0

18

E
Occurrence/Duration Mode Select
1 = Occurrence
0 = Duration

19

PC
Enabled the signaling of performance counter overflow via BP0 pin.

20

INT
Enables the signaling of counter overflow via input to APIC
1 = Enable
0 = Disable

23

INV
Inverts the result of the CMASK condition
1 = Inverted
0 = Non-Inverted

Table 35-46.  MSRs in the P6 Family Processors  (Contd.)

Register 

Address

Register Name

Bit Description

 Hex

Dec