Vol. 3C 35-317

MODEL-SPECIFIC REGISTERS (MSRS)

16

TM_SELECT (R/W) 
Mode of automatic thermal monitor:
0 =  Thermal Monitor 1 (thermally-initiated on-die modulation of the 

stop-clock duty cycle)

1 =  Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no 

effect. Neither TM1 nor TM2 will be enabled.

63:16

Reserved.

1A0H

416

IA32_MISC_ENABLE

Enable Miscellaneous Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.

2:0

Reserved.

3

Automatic Thermal Control Circuit Enable (R/W) 
1 =  Setting this bit enables the thermal control circuit (TCC) portion of 

the Intel Thermal Monitor feature. This allows processor clocks to 

be automatically modulated based on the processor's thermal 

sensor operation. 

0 = Disabled (default). 
The automatic thermal control circuit enable bit determines if the 

thermal control circuit (TCC) will be activated when the processor's 

internal thermal sensor determines the processor is about to exceed its 

maximum operating temperature.
When the TCC is activated and TM1 is enabled, the processors clocks will 

be forced to a 50% duty cycle. BIOS must enable this feature.
The bit should not be confused with the on-demand thermal control 

circuit enable bit.

6:4

Reserved.

7

Performance Monitoring Available (R) 
1 =  Performance monitoring enabled
0 =  Performance monitoring disabled

9:8

Reserved.

10

FERR# Multiplexing Enable (R/W)
1 =  FERR# asserted by the processor to indicate a pending break 

event within the processor 

0 =  Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.
Branch Trace Storage Unavailable (RO)
1 = Processor doesn’t support branch trace storage (BTS)
0 = BTS is supported

12

Processor Event Based Sampling Unavailable (RO) 
1 =  Processor does not support processor event based sampling 

(PEBS); 

0 =  PEBS is supported. 
The Pentium M processor does not support PEBS.

15:13

Reserved.

Table 35-45.  MSRs in Pentium M Processors (Contd.)

Register 

Address

Register Name

Bit Description

 Hex

Dec