Vol. 3C 35-269

MODEL-SPECIFIC REGISTERS (MSRS)

11

Branch Trace Storage Unavailable (RO) 

12

Processor Event Based Sampling Unavailable (RO) 

15:13

Reserved.

16

Enhanced Intel SpeedStep Technology Enable (R/W) 

18

ENABLE MONITOR FSM (R/W) 

21:19

Reserved.

22

Limit CPUID Maxval (R/W) 

23

xTPR Message Disable (R/W) 

33:24

Reserved.

34

XD Bit Disable (R/W) 

37:35

Reserved.

38

Turbo Mode Disable (R/W)

63:39

Reserved.

1A2H

418

MSR_

TEMPERATURE_TARGET

Package

15:0

Reserved.

23:16

Temperature Target (R) 

29:24

Target Offset (R/W) 

63:30

Reserved.

1A4H

420

MSR_MISC_FEATURE_

CONTROL

Miscellaneous Feature Control (R/W) 

0

Core

DCU Hardware Prefetcher Disable (R/W) 
If 1, disables the L1 data cache prefetcher.

1

Core

L2 Hardware Prefetcher Disable (R/W) 
If 1, disables the L2 hardware prefetcher.

63:2

Reserved.

1A6H

422

MSR_OFFCORE_RSP_0

Shared

Offcore Response Event Select Register (R/W)

1A7H

423

MSR_OFFCORE_RSP_1

Shared

Offcore Response Event Select Register (R/W)

1ADH

429

MSR_TURBO_RATIO_LIMIT

Package

Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW)

0

Reserved

7:1

Package

Maximum Number of Cores in Group 0
Number active processor cores which operates under the maximum 

ratio limit for group 0. 

15:8

Package

Maximum Ratio Limit for Group 0
Maximum turbo ratio limit when the number of active cores are not 

more than the group 0 maximum core count. 

Table 35-40.  Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 

06_57H

Address

Register Name

Scope

Bit Description

 Hex

Dec