Vol. 3C 35-255
MODEL-SPECIFIC REGISTERS (MSRS)
1
Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2
Reserved.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal
limit.
6
VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a
processor Voltage Regulator.
7
VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8
Other Status (R0)
When set, frequency is reduced due to electrical or other
constraints.
9
Reserved.
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/Platform-level
power limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/Platform-level
power limiting PL2/PL3.
15:12
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18
Reserved.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec