Vol. 3C 35-251
MODEL-SPECIFIC REGISTERS (MSRS)
65CH
1628
MSR_PLATFORM_POWER_L
IMIT
Platform*
Platform Power Limit Control (R/W-L)
Allows platform BIOS to limit power consumption of the platform
devices to the specified values. The Long Duration power
consumption is specified via Platform_Power_Limit_1 and
Platform_Power_Limit_1_Time. The Short Duration power
consumption limit is specified via the Platform_Power_Limit_2 with
duration chosen by the processor.
The processor implements an exponential-weighted algorithm in
the placement of the time windows.
14:0
Platform Power Limit #1.
Average Power limit value which the platform must not exceed
over a time window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies
with product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
15
Enable Platform Power Limit #1.
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit #1 over
the time window specified by Power Limit #1 Time Window.
16
Platform Clamping Limitation #1.
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit #1 value.
This bit is writeable only when CPUID (EAX=6):EAX[4] is set.
23:17
Time Window for Platform Power Limit #1.
Specifies the duration of the time window over which Platform
Power Limit 1 value should be maintained for sustained long
duration. This field is made up of two numbers from the following
equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17].
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, The unit is specified in
MSR_RAPLPOWER_UNIT[Time Unit].
31:24
Reserved
46:32
Platform Power Limit #2.
Average Power limit value which the platform must not exceed
over the Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration
Power Limit (i.e. Platform Power Limit # 1)
47
Enable Platform Power Limit #2.
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit #2 over
the Short Duration time window.
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec