35-248 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
0
PROCHOT Status (R0)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2
Reserved.
4
Residency State Regulation Status (R0)
When set, frequency is reduced below the operating system
request due to residency state regulation limit.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced below the operating system
request due to Running Average Thermal Limit (RATL).
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from a processor Voltage Regulator
(VR).
7
VR Therm Design Current Status (R0)
When set, frequency is reduced below the operating system
request due to VR thermal design current limit.
8
Other Status (R0)
When set, frequency is reduced below the operating system
request due to electrical or other constraints.
9
Reserved
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package/platform-level power limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package/platform-level power limiting PL2/PL3.
12
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system
request due to multi-core turbo limits.
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system
request due to Turbo transition attenuation. This prevents
performance degradation due to frequent operating ratio changes.
15:14
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec