Vol. 3C 35-233

MODEL-SPECIFIC REGISTERS (MSRS)

18

Power Budget Management Log 
When set, indicates that the PBM Status bit has asserted since the 

log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

19

Platform Configuration Services Log 
When set, indicates that the PCS Status bit has asserted since the 

log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

20

Reserved.

21

Autonomous Utilization-Based Frequency Control Log 
When set, indicates that the AUBFC Status bit has asserted since 

the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

22

VR Therm Alert Log 
When set, indicates that the VR Therm Alert Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

23

Reserved.

24

Electrical Design Point Log 
When set, indicates that the EDP Status bit has asserted since the 

log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

25

Reserved.

26

Multi-Core Turbo Log 
When set, indicates that the Multi-Core Turbo Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

28:27

Reserved.

29

Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

30

Core Max n-core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency 

Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

31

Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

63:32

Reserved.

Table 35-34.  Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based 

on the Broadwell Microarchitecture

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec