35-214 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

22

VR Therm Alert Log 
When set, indicates that the VR Therm Alert Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

23

Reserved.

24

Electrical Design Point Log 
When set, indicates that the EDP Status bit has asserted since the 

log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

25

Reserved.

26

Multi-Core Turbo Log 
When set, indicates that the Multi-Core Turbo Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

28:27

Reserved.

29

Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

30

Core Max n-core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency 

Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

31

Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

63:32

Reserved.

C8DH

3213

IA32_QM_EVTSEL

THREAD

Monitoring Event Select Register (R/W).
if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1

7:0

EventID (RW)
Event encoding:
0x0: no monitoring
0x1: L3 occupancy monitoring
all other encoding reserved.

31:8

Reserved.

41:32

RMID (RW)

63:42

Reserved.

C8EH

3214

IA32_QM_CTR

THREAD

Monitoring Counter Register (R/O).
if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1

61:0

Resource Monitored Data 

Table 35-30.  Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec