Vol. 3C 35-213
MODEL-SPECIFIC REGISTERS (MSRS)
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Reserved.
10
Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system
request due to Multi-Core Turbo limits
12:11
Reserved.
13
Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1
14
Core Max n-core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency
15
Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system
request.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18
Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20
Reserved.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Register Name
Scope
Bit Description
Hex
Dec