Vol. 3C 35-203
MODEL-SPECIFIC REGISTERS (MSRS)
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26
Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30
Reserved.
700H
1792
MSR_UNC_CBO_0_
PERFEVTSEL0
Package
Uncore C-Box 0, counter 0 event select MSR
701H
1793
MSR_UNC_CBO_0_
PERFEVTSEL1
Package
Uncore C-Box 0, counter 1 event select MSR
706H
1798
MSR_UNC_CBO_0_PERFCTR0 Package
Uncore C-Box 0, performance counter 0
707H
1799
MSR_UNC_CBO_0_PERFCTR1 Package
Uncore C-Box 0, performance counter 1
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec