35-200 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30
Reserved.
6B0H
1712
MSR_GRAPHICS_PERF_LIMIT_
REASONS
Package
Indicator of Frequency Clipping in the Processor Graphics
(R/W)
(frequency refers to processor graphics frequency)
0
PROCHOT Status (R0)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2
Reserved.
4
Graphics Driver Status (R0)
When set, frequency is reduced below the operating system
request due to Processor Graphics driver override.
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is low
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Graphics Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to domain-level power limiting.
10
Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11
Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
15:12
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec